Heterogeneous MPSoCs are seen as the solution to tackle performance and power demands in the embedded domain. Their HW and SW complexity necessitates an automatic approach to find the most efficient task-to-processor mapping of parallel applications. Tight power budgets require efficient task mapping, and optimally setting the voltage and frequency of each processor. This paper proposes a novel heuristic that minimises the average power consumption, while meeting performance constraints. Integrated into an industrial SW mapping framework, the applicability is validated using three different case studies and representative benchmarks. Moreover, the power-performance trade-off is discussed. A comparison with the optimal solution complements the evaluation, revealing a loss of 19% by the heuristic, but 700× faster execution.

Virtual platforms have become essential tools for the design of embedded systems. Developers rely on them for design space exploration and software debugging. However, with rising HW/SW complexity and the need to simulate more and more processors simultaneously, the performance of virtual platforms degrades rapidly. Parallel simulation techniques can help to counter this by leveraging multicore PCs, which are widely available today. This work presents a novel parallel simulation approach that is targeted toward acceleration of virtual platforms from the ESL domain. By trading some timing accuracy, multiprocessor virtual platforms can be accelerated by up to 3.4× on regular quad-core workstations.

MPSoCs have evolved into heterogeneous architectures, where general purpose processors are combined with accelerators. Directive-based programming models such as the OpenMP 4.0 accelerator model have emerged as an approach to parallelize and offload code regions to accelerators. However, existing compiler technologies have focused mainly on parallelization, leaving the challenging task of offloading code regions to the developers. In this paper, we propose a novel approach that addresses parallelization and offloading jointly. Results show that our approach is able to speedup sequential embedded applications significantly on a commercial heterogeneous MPSoC, which incorporates a quad-core ARM cluster and an octa-core DSP cluster.

Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi- and many-processor systems-on-chip (MPSoCs). VPs provide unrivaled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware (e.g., bugs originating from races or happening during a processor stand-by state). However, VPs as employed in practice for debugging are generally underutilized. The accompanying debug ecosystem is based mostly on traditional tools, such as step-based debuggers and traces, that fall short to address the enormous complexity of modern MPSoCs and their parallel software. Finding a bug is still largely left to the developer’s experience and intuition, using manual means rather than automated or systematic solutions that exploit the controllability and visibility of VPs. Profiting from VPs for MPSoC software debugging is an open question. To bridge this gap, this article presents a novel framework for debug visualization and execution control that, relying on the many benefits of VPs, helps to identify and test possible concurrency-related bug scenarios. The framework allows examining and steering the target system by manipulating an abstract graph that highlights relevant inter-component interactions and dependencies. The proposed framework reduces the effort required to understand complex concurrency patterns and helps to expose bugs. Its efficacy is demonstrated on (i) a shared memory symmetric multi-processing platform executing Linux and parallel benchmarks, and (ii) a distributed automotive system for driver assistance applications.

In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the use of heterogeneous many-tile architectures. The resulting computing systems are complex: they must be protected against several sources of faults and critical events, and application programmers must be provided with programming paradigms, software environments and debugging tools adequate to manage such complexity. The EURETILE (European Reference Tiled Architecture Experiment) consortium conceived, designed, and implemented: 1- an innovative many-tile, many-process dynamic fault-tolerant programming paradigm and software environment, grounded onto a lightweight operating system generated by an automated software synthesis mechanism that takes into account the architecture and application specificities; 2- a many-tile heterogeneous hardware system, equipped with a high-bandwidth, low-latency, point-to-point 3D-toroidal interconnect. The inter-tile interconnect processor is equipped with an experimental mechanism for systemic fault-awareness; 3- a full-system simulation environment, supported by innovative parallel technologies and equipped with debugging facilities. We also designed and coded a set of application benchmarks representative of requirements of future HPC and Embedded Systems, including: 4- a set of dynamic multimedia applications and 5- a large scale simulator of neural activity and synaptic plasticity. The application benchmarks, compiled through the EURETILE software tool-chain, have been efficiently executed on both the many-tile hardware platform and on the software simulator, up to a complexity of a few hundreds of software processes and hardware cores.

Early design decisions such as architectural class and instruction set selection largely determine the performance and energy consumption of application specific processors (ASIPs). However, making decisions that effectively reflect in high performance require that a careful analysis of the target application is done by an experienced designer. Such process is extremely time consuming, and a confirmation that the processor meets the application requirements can only be extracted after costly architectural implementation, synthesis and simulation. To shorten design times, this work couples High-Level Synthesis (HLS) with pre-architectural performance estimation. We do so with the aim of providing designers with an initial architectural seed together with quantitative feedback about its performance. This enables to perform a light-weight refinement process based on the obtained feedback, such that time-consuming microarchitectural implementation is done only once at the end of the refinement steps. We employed our flow to generate four potential ASIPs for a 1024-point FFT. Estimates validation and gain evaluation is performed on actual ASIP implementations, which achieve performance gains of up to 8.42x and energy gains up to 1.32x over an existing VLIW processor.

Modern cars require powerful multi- and manycore hardware platforms to fulfill the demands of upcoming computationally intensive advanced driver assistance systems. This leads to a distributed hardware/software architecture that poses an unbearable system complexity to designers. Additionally, the strict requirements of new functional safety standards make it extremely difficult to rapidly and comprehensively close the development-evaluation-debug cycle. To overcome these complications, virtual platform technology is a promising approach that provides full hardware/software visibility, controllability and adequate simulation speed at electronic system level. However, for highly heterogeneous systems, such as modern cars, this technology lacks the capability to capture and integrate interactions of multiple subsystems beyond the hardware/software domain. To bridge this gap, this work presents multiple methods to facilitate the integration of virtual platforms into complex heterogeneous multi-domain vehicular simulation systems via the Functional Mock-Up Interface (FMI), the de facto co-simulation standard for automotive. The presented approaches significantly increase the depth of functional safety testing, as holistic car simulation covers cross-domain interactions of its subsystems.

Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi- and many-processor systems-on-chip (MPSoCs). VPs provide unrivalled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware. However, VPs as used for debugging provide only traditional interfaces, such as step-based debuggers and traces, that do little to help with the enormous complexity of MPSoCs and their parallel software. Finding a bug is still largely left to the developer's experience and intuition, using manual means rather than automated solutions. To bridge this gap, this paper presents a novel VP debug visualization and control framework for concurrent software that allows examining and steering the target by means of an abstract representation of its inter-task interactions. Our framework reduces the effort required to understand complex concurrency patterns and helps to expose bugs.

Modern multi- and many-core systems are prone to concurrency-related bugs that surface only at system level. Detecting these bugs might require dealing with low-level hardware (HW) protocols and/or software (SW) inter-task interactions. Virtual platforms (VPs) offer a vehicle to conveniently debug HW/SW functionality, yet developers are mostly limited to manually breakpoint, step and interact with the system. To ease debugging during integration at system level, this paper introduces SWAT, an assertion-based debugging framework that checks and correlates system-wide interactions among HW and SW components. SWAT is used together with VPs to enable detecting HW/SW concurrency bugs with lower effort than traditional manual techniques. Our proposed approach is evaluated on two state-of-the-art platforms running real-world SW stacks.

Writing correct parallel software for modern multi-processor systems-on-chip (MPSoCs) is a complicated task. Programmers can rarely anticipate all possible external and internal interactions in complex concurrent systems. Concurrency bugs originating from races and improper synchronization are difficult to understand and reproduce. Furthermore, traditional debug and verification practices for embedded systems lack support to address this issue efficiently. For instance, programmers still need to step through several executions until finding a buggy state or analyze complex traces, which results in productivity losses. This paper proposes a new debug approach for MPSoCs that combines dynamic analysis and the benefits of virtual platforms. All in all, it (i) enables automatic exploration of SW behavior, (ii) identifies problematic concurrent interactions, (iii) provokes possibly erroneous executions and, ultimately, (iv) detects concurrency bugs. The approach is demonstrated on an industrial-strength virtual platform with a full Linux operating system and real-world parallel benchmarks.

EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This paper focuses on the EURETILE software design flow, which provides a novel programming environment to map multiple dynamic applications onto a many-tile architecture. The elaborated high-level programming model specifies each application as a network of autonomous processes, enabling the automatic generation and optimization of the architecture-specific implementation. Behavioral and architectural dynamism is handled by a hierarchically organized runtime-manager running on top of a lightweight operating system. To evaluate, debug, and profile the generated binaries, a scalable many-tile simulator has been developed. High system dependability is achieved by combining hardware-based fault awareness strategies with software-based fault reactivity strategies. We demonstrate the capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles.

Application Specific Instruction Set Processors (ASIPs) seek for an optimal performance/area/energy trade-off for a given algorithm. In all current design methodologies an architectural model must be first manually created based on designers experience. These models are increasingly refined until the design constraints are met, through several time consuming algorithmic/architecture co-exploration iterations. This paper presents a novel performance estimation approach that shortens the design cycle of existing methodologies by providing an early assessment of the impact of customizations on the achievable performance. The approach does so by eliminating the need for a completely specified architecture, without limiting designer's freedom and without simulating the application repeatedly. Overall, our approach reduces the number of necessary co-exploration iterations, thus increasing design productivity. We validate our approach via two different case studies: a butterfly-enabled ASIP for Fast Fourier Transform computation and a Connected Components Labeling ASIP for computer vision.

The increasing heterogeneity and parallelism of modern multi-processor systems on chip (MPSoCs) demand the evolution of existing debuggers in order to keep software development feasible. Such evolution will only be granted if upcoming software debuggers address key issues like abstraction, retargetability, scalability and convergence of information from different data sources. This paper presents a novel component-based, tree-aggregated debugger architecture which (i) grants flexibility and retargetability to deal with heterogeneous MPSoCs, and (ii) provides a framework to abstract complex details in order to facilitate debug of concurrency bugs. The debugger architecture is evaluated on an industrial-strength MPSoC virtual platform for mobile computing and next generation wireless communications.

Full-system simulators are essential to enable early software development and increase the MPSoC programming productivity, however, their speed is limited by the speed of processor models. Although hybrid processor simulators provide native execution speed and target architecture visibility, their use for modern multi-core OSs and parallel software is restricted due to dynamic temporal and state decoupling side effects. This work analyzes the decoupling effects caused by hybridization and presents a novel synchronization technique which enables full-system hybrid simulation for modern MPSoC software. Experimental results show speed-ups from 2x to 45x over instruction-accurate simulation while still attaining functional correctness.

Due to their good flexibility-performance trade-off, Application Specific Instruction-set Processors (ASIPs) have been identified as a valuable component in modern embedded systems, especially the extensible ones, achieving good cost-efficiency trade-offs. Since the generation of the described hardware is usually automated to a high extent, in order to deliver an ASIP-based design in due time, developers are limited by the performance of the underlying simulation techniques for software development. On the other hand, the Hybrid Processor simulation technology (HySim), which enables dynamic run-time switching between native and instruction-accurate simulation, has reported high speed-up values for some fixed architectures. This paper presents enhanced HySim technology for extensible cores, based on a layered simulation infrastructure. This technology has shown a speed-up on a per-function basis of two orders of magnitude for a realistic MIMO OFDM benchmark on a multi-core platform with customized Xtensa cores by Tensilica.

Advances in process integration, the power wall and end-user application demands have made Multi-Processor Systems on Chip (MPSoCs) a reality. In mobile embedded devices, these systems are heterogeneous in order to cope with stringent real time and energy constraints, which makes them difficult to program, debug and verify. Therefore, a lot of research in industry and academia has focused on providing solutions to this MPSoC programming problem. In this paper we study and extend one of such frameworks, namely, the MPSoC Application Programming Studio (MAPS) [1]. We analyze MAPS retargetability by adding a new backend for a heterogeneous MPSoC with the OSIP hardware scheduler [2]. The new backend exports high level debugging information that is included in an environment for application debugging based on virtual platforms. The extensions are demonstrated on a heterogeneous virtual platform running the JPEG application.

As MPSoCs become key components for the electronics industry, the programmability problem poses an ever increasing burden on the software development process. In addition to the difficulty of writing parallel applications, concurr ency bugs are usually hard to find, understand and reproduce. Programmers writing parallel software need more support from the debugging tools in order to understand harmful effects of concurrent interactions. This paper introduces a debugg er framework that detects concurrency bugs dynamically, base d on user defined bug pattern descriptions. The framework can be configured to address different MPSoCs and different lowlevel APIs.

The spread of technology is mostly possible thanks to the growing presence of Embedded Systems in our everyday lives. Embedded Systems are information processing devices enclosed in a variety of products such as cars, telecommunication or fabrication equipment. These devices must accomplish a large set of requirements and constraints to meet the computational demands of modern applications. As a matter of fact, Embedded Systems are very complex and heterogeneous systems, and this implies very difficult, expensive and time consuming design processes. Although MDE and Hw/Sw codesign are widely used to address the design complexity problem, the lack of design procedures and methodologies joining both concepts restrains their usage as complementary techniques, thus preventing the implementation of faster and more robust design cycles. In this chapter we present a practical semi-automated design flow where both methodologies are merged and exploited to enable a fast design process targeting highly complex Real-Time Embedded Systems, executing several tasks on SoC and MPSoC devices, while allowing the usage of Design Space Exploration, Schedulability Analysis and Estimation techniques.