The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)–based baseline method that exploits OSIRIS for analog design optimization.

The growing demand for always-on intelligence in resource-constrained devices makes edge deployment of deep learning both a necessity and a challenge, requiring platforms that combine efficiency, scalability, and flexibility. RISC-V has emerged as the de facto standard architecture for modern computing platforms at the edge tasked with deep-learning workloads, a trend reinforced by the increasing availability of commercial solutions tailored for inference. This survey delivers a structured taxonomy of the hardware architectures for deep learning at the edge, classified according to how they process data in parallel, represent data, and optimize data movement and whether they implement an application-specific design, and of the supporting software tools, ranging from hardware-software co-design approaches to autotuning and compiler frameworks. Finally, it identifies a set of key findings and outlines the most promising directions for research in the field.

The TEXTAROSSA project aims to bridge the technology gaps that exascale computing systems are currently facing and will be key in the near future to overcome performance and energy efficiency challenges. This project provides solutions for improved energy efficiency by using state-of-the-art cooling and thermal control, seamless integration of heterogeneous accelerators in HPC multi-node platforms, and new arithmetic methods tailored to heterogeneous hardware platforms. Challenges are tackled through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models, and tools derived from European research.

Unrecognized applications running on multi-core SoCs may signal system compromise and increase vulnerability. This paper introduces DUA, a novel methodology to detect the execution of unrecognized software applications on NoC-based multi-core SoCs, leveraging traffic data from the NoC interconnect, or, more broadly, any packet-switched on-chip or interposerlevel interconnect such as a network-in-package. DUA embeds lightweight traffic-monitoring counters into selected routers of the interconnect, and it carries out detection using a one-class support vector machine (OC-SVM) that, due to its unsupervisedlearning nature, is trained only on recognized applications, i.e., applications authorized to run on the system. This allows the DUA methodology to effectively detect unrecognized, never-before-seen applications, including those not considered during training. Identifying the optimal OC-SVM involves exploring a search space that encompasses input features, kernel functions, and hyperparameters. An extensive experimental campaign demonstrates the effectiveness of the methodology in detecting unrecognized applications from the PARSEC benchmark suite on a 16 -core NoC-based SoC. The DUA approach achieves an average accuracy of 85.9% while introducing negligible area and power overheads and not affecting timing, and it shows resilience to queuing-delay noise, indicating generalization across varying traffic conditions.

The design space exploration (DSE) of heterogeneous multi-core systems-on-chip (SoCs) presents a massive challenge due to the vast and complex configuration space, demanding simultaneous optimization of performance, energy efficiency, and resource utilization under diverse constraints. Traditional approaches leveraging analytical models, heuristics, and machine learning (ML) techniques fail to comprehensively cover this space, often yielding suboptimal solutions. The Omega framework, designed for exhaustive DSE of FPGA-based heterogeneous multi-core SoCs, addresses the former limitations by fully exploring the design space and guaranteeing the identification of globally optimal configurations. Omega leverages FPGAs’ dynamic partial reconfiguration to accelerate the DSE drastically and can serve as a golden model for evaluating novel DSE heuristics and ML methods. This manuscript demonstrates the proposed framework’s effectiveness through an extensive experimental campaign on 16-core SoCs with accelerators for up to five different applications, achieving a substantial speedup, of 29 times on average, compared to traditional techniques while ensuring solution optimality. Omega is released as a comprehensive open-source ecosystem, compatible with commercially available FPGA platforms, to facilitate future research and practical adoption, setting a new benchmark for DSE methodologies and providing a robust tool for optimizing next-generation computing platforms.

As the demand for performance and scalability in cloud applications continues to grow, high-performance computing (HPC) facilities increasingly integrate FPGAs to accelerate computational workloads. To fully utilize the extensive resources available on modern high-end FPGAs, it is essential to optimize the allocation of multiple applications on a single device. This article introduces FARMER, a novel online learning methodology that leverages machine learning (ML) to model the throughput of different applications running concurrently on the same FPGA. It combines this with a sequential decision-making strategy and an in-circuit exploration flow based on dynamic partial reconfiguration (DPR) to drastically speed up the exploration of large design spaces. Experimental evaluations across a wide range of representative scenarios, conducted on a real prototyping platform using an AMD Alveo U55C FPGA board, demonstrate that FARMER consistently identifies a feasible solution while exploring less than $\mathbf {0.012\%}$ of the total design space.

Designing and validating efficient cache-coherent memory subsystems is a critical yet complex task in the development of modern multi-core system-on-chip architectures. Rhea is a unified framework that streamlines the design and system-level validation of RTL cache-coherent memory subsystems. On the design side, Rhea generates synthesizable, highly configurable RTL supporting various architectural parameters. On the validation side, Rhea integrates Verilator's cycle-accurate RTL simulation with gem5's full-system simulation, allowing realistic workloads and operating systems to run alongside the actual RTL under test. We apply Rhea to design MSI-based RTL memory subsystems with one and two levels of private caches and scaling up to sixteen cores. Their evaluation with 22 applications from state-of-the-art benchmark suites shows intermediate performance relative to gem5 Ruby's MI and MOESI models. The hybrid gem5-Verilator co-simulation flow incurs a moderate simulation overhead, up to 2.7 times compared to gem5 MI, but achieves higher fidelity by simulating real RTL hardware. This overhead decreases with scale, down to 1.6 times in sixteen-core scenarios. These results demonstrate Rhea's effectiveness and scalability in enabling fast development of RTL cache-coherent memory subsystem designs.

With the ever-increasing demand for performance and scalability in cloud applications, high-performance computing (HPC) facilities are starting to include FPGAs for workload acceleration. To efficiently exploit the massive amount of resources of high-end FPGAs, it is paramount to optimize the allocation of multiple applications on a single device. This paper proposes FARMER, a novel online learning methodology harnessing the power of Gaussian Process regression to model the throughput of different applications running on the same FPGA, and a sequential decision-making approach to explore the available configurations efficiently. Experimental results considering a large variety of representative scenarios tested on a real prototyping platform featuring an AMD Virtex-7 FPGA show that FARMER always finds a feasible solution with an exploration of less than 0.1% of the whole design space.

FPGA-RICH is an FPGA-based online partial particle identification system for the NA62 experiment employing AI techniques. Integrated between the readout of the Ring Imaging Cherenkov detector (RICH) and the low-level trigger processor (L0TP+), FPGA-RICH implements a fast pipeline to process in real-time the RICH raw hit data stream, producing trigger primitives containing elaborate physics information—e.g., the number of charged particles in a physics event—that L0TP+ can use to improve trigger decision efficiency. Deployed on a single FPGA, the system combines classical online processing with a compact Neural Network algorithm to achieve efficient event classification while managing the challenging ∼10 MHz throughput requirement of NA62. The streaming pipeline ensures ∼1 μs latency, comparable to that of the NA62 detectors, allowing its seamless integration in the existing TDAQ setup as an additional detector. Development leverages High-Level Synthesis (HLS) and the open-source hls4ml package software–hardware codesign workflow, enabling fast and flexible reprogramming, debugging, and performance optimization. We describe the implementation of the full processing pipeline, the Neural Network classifier, their functional validation, performance metrics and the system’s current status and outlook.

FPGAs are increasingly utilized in data centers due to their ability to exploit parallelism in computationally intensive workloads. Modern workloads demand the transfer of vast amounts of information, making it essential to optimize communication between FPGAs and memory. This paper introduces a novel benchmarking platform for evaluating DDR4 memory performance in data-center-class FPGAs. The proposed solution features highly configurable traffic generation with complex memory access patterns defined at run time and can be flexibly instantiated on the target FPGA to support multiple memory channels and varying data rates. An extensive experimental campaign targets the AMD Kintex UltraScale 115 FPGA, encompassing up to three memory channels with data rates ranging from 1600 to 2400 MT/s. The results demonstrate the benchmaking platform's capability to effectively evaluate DDR4 performance across various memory traffic configurations.

In the last decades, machine learning techniques have been extensively used in place of classical template attacks to implement profiled side-channel analysis. This manuscript focuses on the application of machine learning to counteract Dynamic Frequency Scaling defenses. While state-of-the-art attacks have shown promising results against desynchronization countermeasures, a robust attack strategy has yet to be realized. Motivated by the simplicity and effectiveness of template attacks for devices lacking desynchronization countermeasures, this work presents a Deep Learning-assisted Template Attack (DLaTA) methodology specifically designed to target highly desynchronized traces through Dynamic Frequency Scaling. A deep learning-based pre-processing step recovers information obscured by desynchronization, followed by a template attack for key extraction. Specifically, we developed a three-stage deep learning pipeline to resynchronize traces to a uniform reference clock frequency. The experimental results on the AES cryptosystem executed on a RISC-V System-on-Chip reported a Guessing Entropy equal to 1 and a Guessing Distance greater than 0.25. Results demonstrate the method’s ability to successfully retrieve secret keys even in the presence of high desynchronization. As an additional contribution, we publicly release our DFS_DESYNCH database 1 1 https://github.com/hardware-fab/DLaTA containing the first set of real-world highly desynchronized power traces from the execution of a software AES cryptosystem.

Side-channel attacks exploit unintended information leakage emitted by cryptographic devices to extract sensitive data. Hiding techniques are a cost-effective countermeasure designed to obfuscate the side-channel leakage and hinder these attacks. Available open datasets rely on artificial models to simulate hiding effects, preventing a realistic assessment of these countermeasures and, thus, leaving a pressing need for datasets offering real-world, obfuscated side-channel measurements. Chameleon introduces the first comprehensive dataset of real-world, obfuscated power traces collected from a RISC-V-based System-on-Chip. The traces are obfuscated using four state-of-the-art hiding techniques: dynamic frequency scaling, random delay, morphing, and chaffing. Chameleon captures real leakage deformations introduced by actual hardware implementations, making it a realistic and valuable tool for evaluating side-channel countermeasures. A key feature of Chameleon is its dual focus on the segmentation and attack stages of the side-channel analysis process. It is the first dataset designed to facilitate the challenging task of segmenting cryptographic operations from obfuscated traces, offering precise metadata that pinpoints the start and end of each operation. The high-quality metadata enables systematic research into segmentation techniques, a critical step often overlooked in previous datasets. Chameleon provides an essential platform for researchers to develop and test new side-channel attacks, highlighting the vulnerabilities of current hiding techniques. By offering a more realistic assessment of countermeasure effectiveness, Chameleon is an invaluable tool for advancing the state-of-the-art in the side-channel evaluation.

The continuous evolution of side-channel analysis motivates a continuous investigation to deliver novel countermeasures. This work presents a hiding countermeasure leveraging a randomized Dynamic Frequency Scaling (DFS) actuator built on top of the clocking resources available in modern FPGAs. In contrast to state-of-the-art DFS-based solutions, our approach is meant to optimize security and performance metrics with a modest increase in power consumption. We experimentally validated our countermeasure on real hardware by comparing it against recently proposed hiding methods employing clock desynchronization. To strengthen our security assessment, we also considered a large variety of state-of-the-art side-channel attacks, including recent deep-learning ones. The experimental results confirm that none of the evaluated attack techniques can breach our protected target, and TLVA shows no information leakage with 10 million traces. The performance overhead is zero, while the power overhead is limited to 1.55x.

Attacks based on side-channel analysis (SCA) pose a severe security threat to modern computing platforms, further exacerbated on IoT devices by their pervasiveness and handling of private and critical data. Designing SCA-resistant computing platforms requires a significant additional effort in the early stages of the IoT devices’ life cycle, which is severely constrained by strict time-to-market deadlines and tight budgets. This manuscript introduces a hardware-software framework meant for SCA research on FPGA targets. It delivers an IoT-class system-on-chip (SoC) that includes a RISC-V CPU, provides observability and controllability through an ad-hoc debug infrastructure to facilitate SCA attacks and evaluate the platform’s security, and streamlines the deployment of SCA countermeasures through dedicated hardware and software features such as a DFS actuator and FreeRTOS support. The open-source release of the framework includes the SoC, the scripts to configure the computing platform, compile a target application, and assess the SCA security, as well as a suite of state-of-the-art attacks and countermeasures. The goal is to foster its adoption and novel developments in the field, empowering designers and researchers to focus on studying SCA countermeasures and attacks while relying on a sound and stable hardware-software platform as the foundation for their research.

APEIRON is a framework encompassing the general architecture of a distributed heterogeneous processing platform and the corresponding software stack, from the low level device drivers up to the high level programming model. Developers can define scalable applications that can be deployed on a multi-FPGA system coding at high level: the APEIRON communication IPs allow low-latency communication between processing tasks deployed on FPGAs, even if hosted on different computing nodes. Thanks to the use of High Level Synthesis tools, tasks are described in high level language (C/C++) while communication is expressed through a lightweight API. The aim of the APEIRON project was to develop a flexible framework that could be adopted in the design and implementation of both “traditional” low level trigger systems and of data reduction stages in trigger-less or streaming readout experimental setups.

AF_XDP is emerging as an easier way to implement zero-copy network bypass applications. This is because it allows mixed-mode deployments, where zero-copy and socket-based applications share the same NIC. However, AF_XDP relies on NIC hardware and driver features, but implementing these features on programmable NICs adds resource overheads and increases development complexity and thus might not be desirable. To address this, we examine the feasibility of using eBPF based kernel extensibility to implement the required features, and report on the tradeoff between an eBPF and a native NIC implementation. Our analysis involved updating the OpenNIC driver to support the loading of eBPF/XDP programs and zero-copy AF_XDP. Our implementation is of independent interest because it makes it easier to develop and evaluate alternate designs for mixed-mode zero-copy deployments, and new NIC accelerated applications. Our implementation is open-sourced

RED-SEA (https://redsea-project.eu/) is a European project funded in the framework of the H2020-JTI-EuroHPC-2019-1 call that started in April 2021. The goal of the project is to evaluate the architectural design of the main elements of the interconnection networks for the next generation of HPC systems supporting hundreds of thousands of computing nodes enabling the Exascale for HPC, HPDA and AI applications while providing preliminary prototypes. The main technological feature is the BXI network, originally designed and produced by ATOS (France). The plan is to integrate in the next release of the network – BXI3 – the architectural solutions and novel IPs developed within the framework of the RED-SEA project. The consortium is composed of 11 well-established research teams across Europe, with extensive experience in interconnects, including network design, deployment and evaluation. Within RED-SEA, INFN is adopting a hardware/software co-design approach to design APEnetX, a scalable interconnect prototyped on latest generation Xilinx FPGAs, adding innovative components for the improvement of the performance and resiliency of the interconnect. APEnetX is an FPGA-based, PCIe Gen3/4 network interface card equipped with RDMA capabilities being the endpoint of a direct multidimensional toroidal network and suitable for integration in the BXI environment. APEnetX design will be benchmarked on project testbeds using real scientific applications like NEST, a spiking neural network simulator.

Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of de-signing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time.

Approximate computing can significantly reduce the energy consumption of computing systems. Mixed-precision hardware architectures and precision-tuning tools for software provide the ability to introduce approximations, but when applied separately, they do not give complete control over the accuracy-energy trade-off. The co-optimization of approximations in hardware and software is a complex task, but it promises considerable benefits. We present a methodology for the fast design-time selection of mixed-precision hardware-software combinations that minimize the energy consumption and the area of the target FPGA-based softcore CPUs with configurable support for floating-point and fixed-point arithmetic. Our approach can evaluate configurations more than 2000 times faster than the alternative approach of using gate-level simulation. On benchmarks from the PolyBench suite the identified hardware-software configurations showed improvement of the energy-to-solution metric ranging from 20% to 95%.

Side-channel attacks allow extracting secret infor-mation from the execution of cryptographic primitives by cor-relating the partially known computed data and the measured side-channel signal. However, to set up a successful side-channel attack, the attacker has to perform i) the challenging task of locating the time instant in which the target cryptographic primitive is executed inside a side-channel trace and then ii) the time-alignment of the measured data on that time instant. This paper presents a novel deep-learning technique to locate the time instant in which the target computed cryptographic operations are executed in the side-channel trace. In contrast to state-of-the-art solutions, the proposed methodology works even in the presence of trace deformations obtained through random delay insertion techniques. We validated our proposal through a successful attack against a variety of unprotected and protected cryptographic primitives that have been executed on an FPGA-implemented system-on-chip featuring a RISC- V CPU.