The 5G core is an important part of a 5G network, and with the exponential growth of connected devices and dynamic traffic conditions, it is essential for the 5G core to be scalable and fault-tolerant. This requirement is even more important with the softwarization of the packet core and cloud-based deployments. This paper presents a comparison of design choices when building a scalable and fault-tolerant 5G core on a Kubernetes-orchestrated cloud platform. Prior work in this direction does not fully explore all design choices, or is not compliant with 3GPP standards. In contrast, we start with a 3GPP-compliant production-grade 5G core, and build multiple variants of cloud-native 5G core components. We leverage Kubernetes’ automatic failover, and auto-scaling capabilities in different ways to make the 5G core scalable and fault-tolerant. We conduct extensive experiments to evaluate the scalability and resilience of various design choices, and to quantify the overheads of cloud deployments. Our work exposes tradeoffs between performance and fault tolerance, and provides insights on how best to design a scalable and fault-tolerant 5G core on Kubernetes.

Recent advances in the Linux kernel, such as eXpress Data Path (XDP) and AF_XDP sockets, enable high-speed packet processing for software NFs while preserving access to kernel features. However, the default AF_XDP implementation in the Linux kernel does not permit easy and performant NF chaining, e.g., zero-copy transfer of packets across NFs co-located on the same host. While prior work has proposed solutions for optimized NF chaining in the context of kernel bypass frameworks like DPDK that operate entirely in userspace, such solutions do not extend easily to AF_XDP, because the AF_XDP datapath is fragmented across the kernel driver and userspace. This paper introduces FLASH, a low-overhead inkernel chaining mechanism for AF_XDP sockets. FLASH enables zero-copy packet transfers for FLASH-native NFs, and single-copy packet transfers for legacy AF_XDP NFs. Further, via integration with K8s, FLASH supports the deployment of unprivileged containerized NFs on cloud platforms. Our work contributes several novel modifications to the AF_XDP datapath in the kernel to implement optimized NF chaining, and provides userspace libraries/APIs to easily build NFs that leverage FLASH. Our evaluations show that FLASH matches the performance of userspace DPDK-based NF chaining frameworks, while outperforming the best available AF_XDP-based alternatives by up to 2.5x in throughput, and achieving the lowest latency among all NF chaining frameworks.

Recent advances like P4 programmable hardware switches in the network, and eBPF programs in the endhost network stack, have significantly improved the ability to customize packet processing pipelines in middleboxes and endhosts, and have enabled the offload of some simple application layer processing to the network. These programming frameworks are typically used for parsing mostly fixed-format network or transport layer headers, and are considered unsuitable for parsing complex application layer headers with variable formats. This paper characterizes the feasibility and limits of parsing complex application layer messages within the restrictive programming environments of P4 switches and eBPF kernel programs, a question that has not received much attention in prior work. We evaluate the feasibility of parsing different types of application message formats on the forwarding path using existing parsing techniques and quantify the overhead of such parsing on the application performance using our optimized implementations of the parsing techniques in eBPF and P4. We use on-path application telemetry, where application layer metrics are extracted by parsing application headers on the packet forwarding path, as a case study to evaluate our implementation. Our evaluation shows that, within the limits of feasibility, on-path network telemetry is more efficient and makes the metrics available sooner than state-of-the-art off-path telemetry systems that mirror packets and analyze them in userspace software.

To leverage the full potential of high-speed network interface cards (NICs), it is essential for network applications to use high-performance packet I/O frameworks. However, porting applications to use these specialized frameworks is a tedious task. While prior work has proposed frameworks to ease the development of network functions over fast packet I/O mechanisms, there has not been much work done to ease the porting of applications that are built to run on the kernel network stack. This paper presents Fastlane, a framework to easily port the "fast path" of traditional network applications to use fast packet I/O mechanisms while retaining the "slow path" to run on the traditional network stack. Fastlane provides APIs by which application developers can configure, use, and switch between different fast packet I/O mechanisms like DPDK and CNDP in the application’s fast path. Additionally, Fastlane provides APIs for the fast path to communicate with the slow path running on the kernel network stack. Fastlane also allows applications to be deployed in an unprivileged Kubernetes pod, easing application development for cloud deployments. We evaluate the effectiveness of Fastlane by porting a production-grade 5G user plane function to use our framework. Our evaluation shows that Fastlane enables developers to build high-performance network applications easily and imposes minimal performance overheads.

Text-based specifications are the de-facto standard for specifying complex multi-tier systems. For example, 3GPP specifications define various interfaces, messages, and message processing at the multiple inter-connected nodes of a 5G system. These standards documents tend to be verbose, and may be ambiguous or inconsistent in places, increasing programmer effort to implement them in a general purpose language. This paper presents Pyramis, a Domain Specific Language (DSL) with suitable high-level abstractions for specifying the interfaces, messages, and processing in a multi-tier system. Pyramis allows programmers to specify multi-tier systems in a concise and precise manner, and enables easy development of software based on the specifications. We also develop a translator with Pyramis that automatically generates optimized, multithreaded C++ code for the various components of the multi-tier system from the specification, and also generates eBPF-based measurement code for computing various performance metrics. We use Pyramis to build several components in the 5G mobile packet core. We show that the specifications written in Pyramis are 2-3x smaller than the actual reference implementation, while the auto-generated C++ code performs on par with a hand-optimized implementation. We believe that Pyramis can eventually replace verbose text specifications like the 3GPP standards documents in telecom systems.

Efforts to improve multicore scalability of network functions (NFs) have traditionally focused on making network stacks scalable via partitioning TCP/IP data structures into percore slices and ensuring flow-to-core affinity, leading to elimination of locking in the network stack while processing an incoming packet. But the above techniques fail to eliminate locking in NFs which store state at the granularity of an application-layer key that does not map to a TCP/IP flow, e.g., NFs in the 5G packet core that store state at the granularity of a mobile subscriber/user, where requests from a user could arrive over multiple flows, or requests from multiple users can arrive on a single flow. Prior work does not allow steering all traffic of a particular user to the same core for such NFs. This paper presents AppSteer, a framework that enables application-aware steering of incoming requests to cores for NFs running on the Linux kernel, in order to localize the requests of a given application-layer entity (e.g., mobile user) to a single core. NFs running over AppSteer can then partition their state into per-core slices and access it in a lockfree manner, leading to better multicore scalability. We evaluate AppSteer by building lockfree versions of production-grade 5G core NFs running on top of AppSteer and show that they have 15-18% higher throughput at 16 cores when compared to their locking-based counterparts.

This paper presents DDIOSim, a cycle-accurate microarchitecture simulator that simulates Data Direct I/O-based network packet processing. Our open-source simulator consists of a front-end trace generator that generates traces of CPU instructions, memory accesses, and network I/O events across multiple networking applications, and a cycle-accurate backend simulator that processes these traces by simulating DDIO operations along with the entire CPU and cache/memory hierarchy. Our simulator can be used to explore various DDIO design and configuration options, and its interactions with other microarchitecture optimizations like cache hierarchy, hardware prefetchers, and DRAM schedulers.

This paper presents DDIOSim, a cycle-accurate microarchitecture simulator that simulates Data Direct I/O-based network packet processing. Our open-source simulator consists of a front-end trace generator that generates traces of CPU instructions, memory accesses, and network I/O events across multiple networking applications, and a cycle-accurate backend simulator that processes these traces by simulating DDIO operations along with the entire CPU and cache/memory hierarchy. Our simulator can be used to explore various DDIO design and configuration options, and its interactions with other microarchitecture optimizations like cache hierarchy, hardware prefetchers, and DRAM schedulers.

The latest generation of 5G telecommunication networks are expected to provide high throughput and low latency while catering to diverse applications like mobile broadband, dense IoT, and self-driving cars. A high performance User Plane Function (UPF), the main element in the 5G user plane, is critical to achieving these performance goals. This paper presents AccelUPF, a 5G UPF that offloads functionality to programmable dataplane hardware for performance acceleration. While prior work has proposed accelerating the UPF by offloading its data forwarding functionality to programmable hardware, the Packet Forwarding Control Protocol (PFCP) messages from the control plane that configure the hardware data forwarding rules were still processed in software. We show that only offloading data forwarding and not PFCP message processing leads to suboptimal performance in the UPF for applications like IoT that have a much higher ratio of PFCP messages to data traffic, due to a bottleneck at the software control plane that configures the hardware packet forwarding rules. In contrast to prior work, AccelUPF offloads both PFCP message processing as well as data forwarding to programmable hardware. AccelUPF overcomes several technical challenges pertaining to the processing of the complex variable-sized PFCP messages within the memory and compute constraints of programmable hardware platforms. Our evaluation of AccelUPF implemented over a Netronome programmable NIC and an Intel Tofino programmable switch demonstrates performance gains over the state-of-the-art UPFs for real-world traffic scenarios.

This paper presents SoftRate , a wireless bit rate adaptation protocol that is responsive to rapidly varying channel conditions. Unlike previous work that uses either frame receptions or signal-to-noise ratio (SNR) estimates to select bit rates, SoftRate uses confidence information calculated by the physical layer and exported to higher layers via the SoftPHY interface to estimate the prevailing channel bit error rate (BER). Senders use this BER estimate, calculated over each received packet (even when the packet has no bit errors), to pick good bit rates. SoftRate’s novel BER computation works across different wireless environments and hardware without requiring any retraining. SoftRate also uses abrupt changes in the BER estimate to identify interference, enabling it to reduce the bit rate only in response to channel errors caused by attenuation or fading. Our experiments conducted using a software radio prototype show that SoftRate achieves 2 × higher throughput than popu-lar frame-level protocols such as SampleRate [4] and RRAA [24]. It also achieves 20% more throughput than an SNR-based protocol trained on the operating environment, and up to 4 × higher throughput than an untrained SNR-based protocol. The throughput gains using SoftRate stem from its ability to react to channel variations within a single packet-time and its robustness to collision losses.

With the advancement of highly network-powered paradigms like 5G, Microservices, etc. which are typically deployed as containers/VMs, there is a growing imperative on the host nodes to perform specialized network tasks like monitoring, filtering, tunneling, load-balancing, etc. While traditionally, these tasks were performed using switches and specialized middleboxes in the network, there is a demand to perform these network tasks on commodity hardware comprising of COTS servers. However, a major challenge is to perform these tasks at low-overhead and high reliability while maintaining low latency, high throughput, and flexibility.

This paper presents the design, implementation, analysis, and experimental evaluation of speak-up , a defense against application-level distributed denial-of-service (DDoS), in which attackers crip-ple a server by sending legitimate-looking requests that consume computational resources ( e.g. , CPU cycles, disk). With speak-up, a victimized server encourages all clients, resources permitting, to automatically send higher volumes of traf(cid:2)c . We suppose that attackers are already using most of their upload bandwidth so cannot react to the encouragement. Good clients, however, have spare upload bandwidth and will react to the encouragement with drastically higher volumes of traf(cid:2)c. The intended outcome of this traf(cid:2)c in(cid:3)ation is that the good clients crowd out the bad ones, thereby captur-ing a much larger fraction of the server’s resources than before. We experiment under various conditions and (cid:2)nd that speak-up causes the server to spend resources on a group of clients in rough proportion to their aggregate upload bandwidth. This result makes the defense viable and effective for a class of real attacks.

The latest generation of 5G telecommunication networks are expected to provide high throughput and low latency while catering to diverse applications like mobile broadband, dense IoT, and self-driving cars. A high performance User Plane Function (UPF), the main element in the 5G user plane, is critical to achieving these performance goals. This paper presents AccelUPF, a 5G UPF that offloads functionality to programmable dataplane hardware for performance acceleration. While prior work has proposed accelerating the UPF by offloading its data forwarding functionality to programmable hardware, the Packet Forwarding Control Protocol (PFCP) messages from the control plane that configure the hardware data forwarding rules were still processed in software. We show that only offloading data forwarding and not PFCP message processing leads to suboptimal performance in the UPF for applications like IoT that have a much higher ratio of PFCP messages to data traffic, due to a bottleneck at the software control plane that configures the hardware packet forwarding rules. In contrast to prior work, AccelUPF offloads both PFCP message processing as well as data forwarding to programmable hardware. AccelUPF overcomes several technical challenges pertaining to the processing of the complex variable-sized PFCP messages within the memory and compute constraints of programmable hardware platforms. Our evaluation of AccelUPF implemented over a Netronome programmable NIC and an Intel Tofino programmable switch demonstrates performance gains over the state-of-the-art UPFs for real-world traffic scenarios.

This demonstration will present the operation and main features of the 5G Core software system based on 3GPP Release 16. The system is being developed as part of the Indigenous India 5G testbed project, led by IIT Madras. The core software is based on Network Function Virtualization concepts and the Service Based Architecture (SBA). The main features to be demonstrated in the current version will be UE (de)registration, PDU session establishment and release.

Emerging 5G applications require a dataplane that has a high forwarding throughput and low processing latency, in addition to low cost and power consumption. To meet these requirements, the state-of-the-art 5G User Plane Functions (UPFs) are built over high performance packet I/O mechanisms like the Data Plane Development Kit (DPDK), and further offload some functionality to programmable dataplane hardware. In this paper, we design and implement several standards-compliant UPF prototypes, beginning with a software-only DPDK-based UPF, progressing to designs which offload different functions to programmable hardware. We evaluate and compare the performance of these designs, to highlight the costs and benefits of these offloads. Our results show that offload techniques employed in prior work help improve performance in certain scenarios, but also have their limitations. Overcoming these limitations and fully realizing the power of programmable hardware requires offloading more complex functionality than is done today. Our work presents a preliminary implementation towards a comprehensive programmable dataplane-accelerated 5G UPF.

Multi-access Edge Computing (MEC) is an evolving technology and considered as one of the critical enablers for technologies to meet the IMT definition of 5G communications. It integrates the service provider's network with the high-performance computation facility to cater to various applications such as augmented reality, vision applications, etc., at the network edge. Thus, reducing the overall latency and preserving the bandwidth to send the complete data to the centralized data centers for processing instead. Furthermore, MEC opens up tremendous business opportunities for telecommunication companies by offering a service platform for deploying various services specific to consumers and industry at the network edge. In this work, we have demonstrated a full-fledged MEC architecture, including its entities, and integrated with 5G core following ETSI 5G specification with an application deployment use-case. The various MEC and 5G core components are instantiated in the virtual machine as a guest; the complete data path and control path is established between all core components following a service-based architecture. The MEC system developed is a part of the indigenous 5G Test-Bed project and follows the ETSI architecture. The developed system is suitable for executing various applications that require data offloading, extensive storage, and computing resources. Thus, our working MEC system establishes a proof of concept and closely resembles a real-world deployment of MEC system in 5G environment.

Several novel userspace network stacks have been proposed in recent research to overcome the limitations of the Linux network stack in providing high-performance I/O for Virtual Network Functions (VNFs). In this paper, we evaluate the performance of several state-of-the-art network stacks in the context of the VNFs of the 5G mobile packet core. The VNFs in the 5G core are several times more compute-intensive than the VNFs used to benchmark network stacks in prior work, given the need to perform user authentication and other such cryptographic operations. Our evaluation shows that while modern stacks outperform the Linux kernel stack over I/O intensive VNFs (as observed in prior work), the performance gap is not as wide in the case of CPU-intensive VNFs of the 5G core. We also find that the packet core VNFs can obtain up to 67% higher performance if the network stack could partition traffic to CPU cores at the granularity at which VNFs maintain state (mobile subscriber in this case), enabling a lockfree architecture within the VNF. The insights from our work can help us design a network stack that is better suited for compute-intensive VNFs such as those in the 5G core.

Recent architectures of the mobile packet core advocate the separation of the control and dataplane components, with all signaling messages being processed by the control plane entities. This paper presents the design, implementation, and evaluation of TurboEPC, a redesign of the mobile packet core that revisits the division of work between the control and data planes. In TurboEPC, the control plane offloads a small amount of user state to programmable dataplane switches, using which the switches can correctly process a subset of signaling messages within the dataplane itself. The messages that are offloaded to the dataplane in TurboEPC constitute a significant fraction of the total signaling traffic in the packet core, and handling these messages on dataplane switches closer to the end-user improves both control plane processing throughput and latency. We implemented the TurboEPC design using P4-based software and hardware switches. The TurboEPC hardware prototype shows throughput and latency improvements by up to 102x and 98% respectively when the switch hardware stores the state of 65K concurrent users, and 22× and 97% respectively when the switch CPU is busy forwarding dataplane traffic at linerate, over the traditional EPC.

Recent architectures of the mobile packet core advocate the separation of the control and dataplane components, with all signaling messages being processed by the control plane entities. This paper presents the design, implementation, and evaluation of TurboEPC, a redesign of the mobile packet core that revisits the division of work between the control and data planes. In TurboEPC, the control plane offloads a small amount of user state to programmable dataplane switches, using which the switches can correctly process a subset of signaling messages within the dataplane itself. The messages that are offloaded to the dataplane in TurboEPC constitute a significant fraction of the total signaling traffic in the packet core, and handling these messages on dataplane switches closer to the end-user improves both control plane processing throughput and latency. We implemented the TurboEPC design using P4-based software and hardware switches. The TurboEPC hardware prototype shows throughput and latency improvements by up to 102x and 98% respectively when the switch hardware stores the state of 65K concurrent users, and 22× and 97% respectively when the switch CPU is busy forwarding dataplane traffic at linerate, over the traditional EPC.