This letter presents the first experimental demonstration of a new type of silicon-integrated sub-terahertz (THz) waveguide, based on porous silicon (PS). The waveguide (WG) is realized on an ultralow-resistivity (ULR) silicon substrate using a single-step electrochemical anodization that codefines material and geometry, eliminating deep reactive-ion etching (DRIE) and wafer bonding. A coplanar-waveguide-to-PS-WG transition enables direct on-wafer characterization. The fabricated PS WG is targeted for D-band operation and exhibits a measured attenuation loss of 0.7 dB/mm at 140 GHz, in excellent agreement with full-wave simulations. This confirms the validity of the codesign approach. Combining low loss, simplified fabrication, and inherent material tunability, the proposed PS WG offers a promising route toward highly integrated sub-terahertz passive components and enables future gas and biosensing applications.

A microelectromechanical system (MEMS) silicon-on-insulator (SOI) differential pressure sensor, integrating a Wheatstone full bridge with four thin monocrystalline Si mesa piezoresistors located at the edges of an ultrathin (2.5 mu m) and miniaturized (0.18 mm(2)) Si3N4/SiO2 membrane, is thoroughly investigated by both electrical and mechanical measurements. A comprehensive model is proposed to analyze the physical phenomena and correlate the electrical and mechanical properties. The pressure sensor demonstrates excellent electrical and mechanical performances under positive backside differential pressure, that is, for upward deflection, at supply voltages of 5 and 10 V. Under 10 V, the output voltage exhibits a linear increase from 0 to 100 kPa, achieving a high sensitivity and a mechanical figure of merit of 0.461 mu V/V/Pa and 2.56 ppm/Pa/mm(2), respectively, with a full-scale (FS) total nonlinearity error (NL) up to 0.78% FS. Analyzing the topographic measurements by deflection-pressure and stress-strain methods, Young's modulus and residual stress are extracted to be similar to 116 GPa and 82 MPa, respectively. According to a comprehensive model, the optimal electrical performance of the pressure sensor is attributed to a high strain increase with pressure thanks to an ultrathin miniaturized membrane and piezoresistors closer to the membrane bottom surface. The relatively high total nonlinearity is caused by a dominant mechanical nonlinearity, which can be reduced in the future by improving the gauge positions and alignment.

work investigates the robustness of an ultrathin backside-illuminated (BSI) silicon-on-insulator (SOI) single-photon avalanche diode (SPAD) against gamma-ray irradiation for space applications. Experimental results demonstrate a breakdown voltage shift in the studied SPAD from 10.17 to 9.95 V after a total ionizing dose (TID) of 132 krad(Si). An increase in dark count rate (DCR) from 1490 to 2700 cps/mu m2 at 1 V excess bias is shown at this dose. TCAD simulations explain the role of the oxide-trapped charges, induced by irradiation in the insulating layer surrounding the active region, on the SPAD performance. These trapped charges shift the peak electric field, leading to premature breakdown while the extension of the active area affected by impact ionization increases the DCR. Further simulations show that implementing a perimeter-gated structure and reducing oxide thickness can effectively mitigate these effects by leveraging capacitive effects, preventing a breakdown voltage shift. The perimeter gate (PG) lowers the simulated DCR after irradiation from 2700 to 1365 cps/mu m(2), thereby enhancing the radiation resilience of ultrathin SOI SPADs beyond a TID of 132 krad(Si).

This paper reports the design, integration, modelling and characterization of single crystalline (c-Si) resistors on a 3.6 $\mathrm{\mu }$m-thick and 2.7 mm-diameter polyimide MEMS membrane. We propose a straightforward top-down fabrication scheme to integrate any microfabricated devices onto a flexible membrane. A bulge-test setup is assembled to measure the deflection of the membrane under a white light interferometer. In addition, a finite elements method (FEM) model is introduced to predict the behavior of the membrane under increasing pressure up to 80 kPa. The parameters of the FEM simulation are tuned with the deflection results to extract the strain tensor, showing a maximal biaxial strain of 0.37% at 80 kPa in the 300 nm-thick c-Si devices. Raman spectroscopy is finally employed to confirm the FEM results by comparing the estimated Raman peak-shift with actual Raman measurements. The shift predicted using phonon-deformation potential (PDP) theory shows excellent agreement with the experimental validation, giving confidence in the FEM model.

This work presents a SPICE compact macro-model for the transient intrinsic response of a Single-Photon Avalanche Diode (SPAD) pixel to a light pulse. The physical phenomena and related parameters are evaluated by performing mixed-mode TCAD simulations. The model is composed of three equivalent diode sub-circuits with their respective junction capacitance adapted to describe the successive mechanisms conditioning the intrinsic transient photo-response of the SPAD. After considering a light pulse, the SPICE model fairly reproduces the TCAD fast current pulse with a peak of about 2mA and a time constant of about 3ps, followed by a diffusion current response with a time constant of 35ps. It results in a self-sustaining current of about 8µA with a diode cathode voltage of 6.3V. Finally, it models the slow recharge through the quenching resistor with a time constant of 264ns. The proposed model facilitates the design of a compatible read-out circuit, e.g., with active recharge, by accurately reproducing physical current and voltage responses.

Consistently with recently published theoretical work, we experimentally demonstrate that, in electronic devices exhibiting strongly nonlinear current-voltage characteristics, the white noise cannot be purely Gaussian, as predicted by the stochastic thermodynamic relations. Micro-fabricated silicon single-photon avalanche diodes exemplify this result. Relying on high-accuracy time-domain noise measurements, we go beyond the conventional characterization of fluctuations in terms of mean and variance only by also assessing the third moment (skewness).

In this work, we compare the performance of a large square spiral inductor with an area of 1.08×1.08 mm 2 and an operating frequency of a few hundred MHz, integrated atop four different types of silicon substrates. Measured and simulated results show that the high-resistivity (HR) substrate with a trap-rich (TR) layer yields significantly better performance in terms of quality factor, resonant frequency, self-inductance, and substrate capacitance than the HR or standard Si ones. These results approach those simulated for the same structure suspended on a MEMS membrane. Moreover, the inductor characteristics exhibit good stability under a back-contact voltage varying between -100 V and +100 V in the HR-TR case.

This study aims to analyze and compare the characteristics of Metal-Insulator-Metal (MIM) capacitors, focusing on the effect of the stacking selection of thick dielectric materials, for future applications requiring robustness to high voltages and temperatures. The 300 nm-thick dielectric stacks under investigation include SiO 2 and Si 3 N 4 materials deposited using plasma-enhanced chemical vapor deposition (PECVD) at a high temperature (300°C), as well as Al 2 O 3 deposited through reactive sputtering at room temperature. The experimental results presented in this work highlight the importance of the stacking choice of these dielectric materials for minimizing the residual stress and the temperature coefficient of capacitance (TCC) and enhancing the overall dielectric constant. These factors contribute to achieving increased capacitance density, with mechanical and electrical resistance to harsh conditions.

This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365 degrees C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

A strain sensor inspired by a Widlar self-biased current source topology called fl -multiplier is developed to obtain a strain-dependent reference current with high supply rejection. The sensor relies on the piezoresistive effect in the silicon MOS transistors that form the current reference circuit. The device behavior is analytically computed and verified with experimental measurements under four-point bending test. A basic implementation with an integrated resistor reaches a strain sensitivity of 2.54 nA/mu epsilon (gauge factor of 324) for a temperature sensitivity of 52.06 nA/degrees C. A more advanced full-transistor circuit based on current subtraction principle is furthered implemented in order to reach strain sensitivity up to 12.02 nA/mu c (gauge factor of 1773) and temperature sensitivity of -28.72 nA/degrees C. This implementation includes a CMOS active load to tune the strain and temperature sensitivities with a total power consumption between 20 and 150 mu W.

This work introduces a new measurement methodology for enhancing gas detection by tuning the magnitude and polarity of back-gate voltage of a field-effect transistor (FET)-based sensor. The aim is to simultaneously strengthen the sensor response and accelerate the sensor recovery. In addition, this methodology can consume less energy compared with conventional measurements by direct current bias. To illustrate the benefits of the proposed methodology, we fabricated and characterized a polypyrrole/graphene (PPy/G) FET sensor for ammonia (NH3) detection. Our experiment, simulation and calculation results demonstrated that the redox reaction between the NH3 molecules and the PPy/G sensitive layer could be controlled by altering the polarity and the magnitude of the back-gate voltage. This proof-of-principle measurement methodology, which solves the inherent contradiction between high response and slow recovery of the chemiresistive sensor, could be extended to detect other gases, so as to improve global gas measurement systems. It opens up a new route for FET-based gas sensors in practical applications.

We present the world's thinnest backside illuminated (BSI) single-photon avalanche diode (SPAD) with a silicon (Si) thickness of 650 nm fabricated in complementary metal-oxide-semiconductor (CMOS) compatible silicon-on-insulator (SOI) technology. The well-optimized doping profile is exploited in this square-shaped BSI SPAD with ultrathin Si body consisting of n++/p-well and n-well guard ring (GR) to outstandingly improve detection efficiency in ultraviolet (UV) spectral range. This BSI SPAD exhibits a low leakage current (≈0.1pA) and a low breakdown voltage (8.5V) at room temperature (RT). A low dark count rate (DCR) of 156.8cps/μm2 at 3V excess bias is estimated at RT. A peak quantum efficiency (QE) of 96.41% is also measured under a wavelength of 423 nm at 4V. This BSI SPAD indicates a peak photon detection probability (PDP) of 69.51% upon a wavelength of 423 nm at 3V excess bias. A significant expansion of the UV sensitivity down to a wavelength of 291 nm is represented with a PDP of 15.56% at 3V excess bias. To the best of our knowledge, the detection efficiency of this ultrathin BSI SPAD in the UV wavelength regime down to 291 nm is the best result ever reported for Si-based BSI SPAD in spite of the absence of an integrated CMOS circuitry.

In this paper, negative transconductance (NTC) behavior in molybdenum disulfides (MoS2) field effect transistors (FETs) is investigated. Combining experimental observation and numerical analysis, we demonstrate that positive shift in the device transfer curves results from the electron trapping/de-trapping processes, where the defect densities at the MoS2/SiO2 interface are reduced when the temperature T decreases from 300 to 200 K. Moreover, the main types of defects that affect the device electrical performance are the interface defect and bulk sulfur vacancy VS in which VS induces the p-type doping effect. While decreasing T below 100 K, NTC occurs when their active layer thickness t (=41 and 35 nm) is larger than the Debye length λ (28 nm). Considering the n-type doping effect induced by the interface defects and the p-type doping caused by the bulk S vacancies, these two opposite doping regions are carefully implemented in simulation at T = 70 K. A vertical barrier induced by the inhomogeneous electron distribution enlarges with the increased gate bias VGS and, thereafter, leads to the unconventional increase in the contact and total resistances with t > λ. While t ≦ λ, the barrier and NTC behavior disappear. The current IDS and transconductance g obtained from the simulation confirm the low-temperature NTC mechanism related to the defects as discussed above. The material defects and physical origin of NTC discussed in the multilayer MoS2 transistors provide the theoretical foundation for designing and realizing novel structures of functional devices via defect engineering in the two-dimensional FET.

We have developed a straightforward die-level thinning process suitable for Silicon-On-Insulator (SOI) dies. The process has been demonstrated on SOI CMOS die assembled on rigid and flexible PCBs using previously-developed anisotropic conductive adhesive flip-chip method. Unlike standard wafer-level thinning processes, in the demonstrated process the full thickness SOI die is directly mounted on PCB and after that thinned. The demonstrated process is simple and robust; it comprises fewer process steps compared to conventional die thinning process. The ultra-thinning process has no effects on the assembly integrity and device performance.

This paper demonstrates a procedure for total insitu recovery of on-membrane n-type MOSFET from Total Ionizing Dose (TID) defects, due to the exposure to gamma radiation. After a total dose of 348 krad (Si), several annealing steps were applied using an integrated micro-heater with a maximum temperature of 364 °C. The electrical characteristics of the transistor are recorded initially in normal conditions, after irradiation and then after each step of the thermal annealing. The electro-thermal annealing of the transistor allowed a total recovery of the original characteristics after a major shift due to radiation-induced defects. Power Spectral Density (PSD) of noise measurements showed a clear domination of the Random Telegraph Noise (RTN) behavior due to the creation of oxide defects after irradiation. After annealing, the RTN behavior vanishes with a further important decrease of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing.

Silicon membrane strip photodetectors are fabricated based on thin silicon-on-insulator (SOI) wafers. The thin SOI wafer is realized by exploiting a thinning process on backside. Such detectors can be implemented in proton-beam position detection because its ultra-thin membrane substrate can reduce beam scattering and offer the considerable advantages of higher radiation hardness. A p-spray implantation process is typically performed at the silicon surface between the n+-strips in order to insulate them, without requiring an extra photolithographic mask. In this paper, the sources of leakage current in the detector are first studied by considering both activation energy and simulation analysis in Silvaco TCAD. While the device is operating below avalanche breakdown voltage, the Shockley–Read–Hall process and trap-assisted-tunneling process are dominantly contributing to leakage current. The dominant breakdown voltage is attributed to the premature breakdown in the junction of p−spray/n+ region. The shift of this breakdown voltage under repeated avalanche processes is analyzed in-depth by both experiments and simulations, as a function of temperature and electrical stress conditions, which are introducing an important reliability problem. The electrical stress can be attributed to an increase in fixed charge density at the Si/SiO2 interface. The breakdown voltage finally increases by 4 V after successive avalanche breakdowns as a function of the applied excess bias voltage beyond breakdown voltage.

In this work, we present a way to improve piezoresistive MOSFET strain gauges using Lock-In principle. This reduces the influence of 1/f-noise, showing a Limit of Detection (LoD) reduction from 474 (42) μϵ for current measurements to 40.5 (15) μϵ for Lock-In measurements at 10 μA (100μA) bias. This 1/f-noise reduction also allows for using more efficiently averaging, leading to a 50-fold improvement from 387 (30) μϵ for current measurements to 7.8 (2.4) μϵ for Lock-In, with 100 samples averaging.

In this work, we explore the output-conductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the current-voltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

Ultra-thin silicon-on-insulator-based sensors are presented, featuring a thickness of less than 20 μm, as new integrable items for wearable physical and physiological ultra-low-power applications. Depending on the Si thickness, the back contact realization and the bias conditions, they can be optimized for thermal sensing or optical sensing in the UV-VIS light band. A lateral PIN diode with a transparent graphene back gate shows a maximum responsivity of 0.18 A/W at 390 nm wavelength, and a high sensitivity of ~2.28 mV/°C at fixed 0.01 μA low bias current, whereas a vertical PN strip diode with an Al back contact extends the optical responsivity to the visible range (with e.g. 0.24 A/W at 555nm wavelength when biased at -2 V) and achieves a high-temperature sensitivity using constant reverse voltage method.

In this article, we are presenting a new classification methodology for high resolution membrane based MEMS piezoresistive pressure sensors embedded in Internet of Things (IoT) nodes or in body-implanted devices. This is based on a new figure of merit (FoM) that includes the four key parameters as the power consumption, the area, the noise and the sensitivity of the transducer. The proposed classification allows to directly evaluate, based on power consumption and area requirements, the ultimate limit of detection that can be reached by a proposed technology. The derivation of the proposed FoM is validated based on wide survey and comparisons of literature results. It shows that, until now, wet etching technics for membrane release still allow for reaching higher performances than reactive ion etching.