Dopants diffusion, activation and pile-up due to rapid thermal annealing of implanted Al and B in a thin (∼200Å) Si cap layer on top of Si 1-x-y Ge x C y layer were studied. Experimental results show that both the lattice strain and differential diffusion flux can cause atomic pile-up at the interface and the evidences of those effects were shown independently to each other in this paper. In addition, the pile-up can be extended from the interface to the surface by incorporating C in the underlying layer where B diffusion is much less than in the cap Si. Material analysis shows that both B atomic and activated concentrations in the Si cap layer are increased by 50 %, which suggests that the dopant activation can be increased and junction depth can be decreased at the same time using the inserted Si 1-x-y Ge x C y diffusion blocking layer.

It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies, there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length variation can improve core matching in multicore designs.

Tensile-strained Si on relaxed Si1−xGex buffers has emerged as an important channel material for improving CMOS performance. The ability of tensile-strained Si to dramatically improve MOSFET drive currents has received much attention in the literature in recent years, but little is known about its reliability characteristics. In this review we discuss some of the issues that should be considered in the analysis of hot-electron reliability of strained Si n-channel MOSFETs.

The SiGeC ternary alloy seems to be an attractive material system for Si-based device applications, because the incorporation of a small amount of C in the high-mobility SiGe layer offers an additional degree of freedom for tuning the bandgap, band offsets and the lattice strain in group IV heterostructures. In this work, detailed low-frequency noise (LFN) results in SiGeC pMOSFETs are presented. Our experimental results in saturation regime of the SiGe MOSFET show that the noise in SiGeC MOSFETs at gate bias \V-GS-V-T\<0.4V can be referred to the gate terminal as a noise voltage S-VG=V-G(2), which implies (DeltaN) fluctuation with correlated noise in the cap and SiGeC channel currents. Overall, the trend shows that the gate referred noise voltage scales inversely with. the gate area, and that the variation of the noise level has log-normal distribution. Therefore, the noise in SiGeC MOSFETs can be expressed as S=S(avg)(.)exp(t-sigma(Np)), where t=+/-1,...,+/-3 is a coefficient selected for desired confidence probability of 0.6,...,0.99 respectively, and sigma is the standard deviation of the log-normal distribution of the noise level around its average S-avg, later given by (DeltaN-Deltamu) fluctuation in the cap layer and SiGeC channel of pMOSFET.

As the challenges to conventional scaling become more difficult, strained Si/relaxed Si1-xGex structures provide a viable means of improving CMOS performance. For NMOSFETs, the tensile strain in pseudomorphic Si on relaxed Si1-xGex splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced inter-valley scattering. In this paper, in addition to confirming enhanced performance for strained Si NMOSFETs, we present hot-electron degradation characteristics for the first time, showing improvement over unstrained Si.

Strained-Si/relaxed-Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For nMOS devices, the tensile strain in pseudomorphic Si on relaxed-Si/sub 1-x/Ge/sub x/ splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced intervalley scattering. In this paper, in addition to confirming enhanced performance for biaxial-strained-Si nMOS, we present hot-electron degradation characteristics for the first time, showing improvement over bulk Si.

We report that drive current enhancement and higher mobilities than the universal mobility in compressively strained Si1−xGex on Si surface-channel p-type metal-oxide–semiconductor field-effect-transistors (PMOSFETs) with HfO2 gate dielectric, for gate lengths (LG) down to 180nm. 36% drive current enhancement was achieved for Si0.8Ge0.2 channel PMOSFETs compared to Si with HfO2 gate dielectric. We demonstrate that using SiGe in the channel may be one way to recover the mobility degradation due to the use of HfO2. Buried-channel PMOSFETs with a Si cap layer and SiO2 gate dielectrics were also studied. 41% peak mobility enhancement in Si1−xGex channel PMOSFETs was observed compared to Si channel PMOSFETs. 17% drive current enhancement was achieved for 70nm channel length (LG) Si0.9Ge0.1 PMOSFETs with SiO2 gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects (SCE) were achieved for the buried-channel Si1−xGex devices with LG=70nm, by controlling Si cap thickness, compared to the Si channel devices. Drive current enhancement without significant SCE and leakage current degradation was observed in this work.

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si 1− x Ge x /Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si 1− x Ge x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length ( L G ) Si 0.9 Ge 0.1 PMOSFETs with SiO 2 gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si 1− x Ge x devices with L G =70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.

A nickel silicide process for Si1-xGex, Si1-x-yGexCy, and. Si1-yCy alloy materials compatible with Si technology has been developed. Low-resistivity-phase (12-20 muOmega cm) nickel silicides have been obtained for these alloys with different low sheet-resistance temperature windows. The study shows that thin (15-18 nm) silicide layers with high crystalline quality, smooth silicide surface, and smooth interface between silicide and the underlying material are achievable. The technique could be used to combine the benefits of Ni silicide and Si1-xGex, Si1-x-yGexCy, and Si1-yCy alloys. The technique is promising for Si or Si1-xGex, Si1-x-yGexCy, and Si1-yCy alloy-based metal-oxide semiconductor, field-effect transistors (MOSFETs) or other device applications.

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.

Si1−yCy alloy layers deposited on (100) Si form a tensile-strained layer, similar to strained-Si on a relaxed SiGe buffer. We present the results of fabrication of heterojunction metal oxide semiconductor field effect transistor (MOSFET) devices using Si1−yCy alloy layers, deposited by UHVCVD. By developing a low temperature process flow (<750 °C), processing concerns for these types of films are alleviated. We present the results of Si1−yCy/Si heterojunction NMOSFET and PMOSFET devices. For small amounts of C (∼0.5%), we found significant enhancement for PMOSFET devices; however, NMOSFET devices showed significant degradation. We show that with increasing fields and C concentrations, device performance may be hampered by alloy scattering in spite of the favorable bandstructure.

Step and Flash Imprint Lithography (SFIL) is an alternative lithography technique that enables patterning of sub-100 nm features at a cost that has the potential to be substantially lower than either conventional projection lithography or proposed next generation lithography techniques. SFIL is a molding process that transfers the topography of a rigid transparent template using a low-viscosity, UV-curable organosilicon solution at room temperature and with minimal applied pressure.(1) Employing SFIL technology we have successfully patterned areas of high and low density, semi-dense and isolated lines down to 20 run,(2) and demonstrated the capability of layer-to-layer alignment.(3) We have also confirmed the use of SFIL to produce functional optical devices including a micropolarizer array consisting of orthogonal 100 nm titanium lines and spaces fabricated using a metal lift-off process.(4) This paper presents a demonstration of the SFIL technique for the patterning of the gate level in a functional MOSFET device.

A nickel silicide process for Si 1-x Ge x , Si 1-x-y Ge x C y , and Si 1-y C y alloy materials compatible with Si technology has been developed. Low-resistivity-phase (12–20 µΘ cm) nickel silicides have been obtained for these alloys with different low sheet-resistance temperature windows. The study shows that thin (15–18 nm) silicide layers with high crystalline quality, smooth silicide surface, and smooth interface between silicide and the underlying material are achievable. The technique could be used to combine the benefits of Ni silicide and Si 1-x Ge x , Si 1-x-y Ge x C y , and Si 1-y C y alloys. The technique is promising for Si or Si 1-x Ge x , Si 1-x-y Ge x C y , and Si 1-y C y alloy-based metal-oxide semiconductor, field-effect transistors (MOSFETs) or other device applications.

Deep submicron (0.35 μm) strained Si1−xGex buried channel p-MOSFETs with a Ge concentration up to 50% were simulated using the MEDICI device simulator. A buried channel structure offers several benefits over a surface channel structure without a Si cap. Simulation results show that the maximum drain current increases monotonically with the Ge mole fraction. The drive current enhancement is more than 300% for Si0.5 Ge0.5 over Si. Subthreshold characteristics were analyzed for different Ge mole fractions in this study. The effects of Si cap layer thickness and Si1−xGex channel thickness on drive current and gate voltage operating window were analyzed. The simulation results show that the drive current is the highest when the Si1−xGex layer thickness is between 100 and 300 Å and that Si1−xGex layer thickness can be as low as 50 Å with less than 10% penalty in the drive current, for structures with a 50 Å Si cap layer.

SiGe source heterojunction p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) have been used before to suppress the short channel effect for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the heterojunction. In this letter, we discuss a SiGe source heterojunction vertical p-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering (DIBL) effect and floating body effect are still suppressed. The electrical characterization of the device shows it exhibits higher drive current and less DIBL compared with a Si control device.