Hot carrier induced drain current degradation can be monitored using sensitive charge-pumping measurements, particularly after worst case ageing conditions. This measurement technique permits stress experiments close to normal operating conditions. Using the charge-pumping measurements and simple I-V models, the device lifetime is calculated from low voltage stress experiments. Thus, lifetime prediction is obtained with higher accuracy than with classical methods, which are based on extrapolations from high voltage injections.

In this work, we present a new method to determine the Dito constant, which is involved in a mobility reduction law. From different types of static aging measurements, the channel length variation is calculated, using the correct value of Dito. It is thus demonstrated that negative charge trapping tends to reduce the channel length whereas positive charge trapping increases this length.

The use of gate isolated test transistors can lead to the creation of process-induced charges which cannot occur on transistors implemented on circuits. A test structure has been designed to separate the intrinsic process related defects which can result in yield losses on circuits, and the charges or states created in the devices usually used in test patterns. With the use of this collection test structure (CTS), the influence of the different process steps in terms of creation of charges can be identified; in particular, the role of the last steps can be pointed out

The authors discuss the influence of back oxide trapped charges on the degradation of the output characteristics of irradiated SOI PMOS transistors. It is found that a positive back gate bias during gamma irradiation promotes an accumulation of trapped holes at the Si-SiO/sub 2/ interface in the buried oxide. The induced parasitic kink effect, which is usually present in SOI NMOS, has been observed and characterized in a PMOS transistor. These results, explained by the increased electric field near the drain, are confirmed by a 2-D analysis. This phenomenon, related to P-channels, should be taken into account for analogical device and circuit optimization.< >

The drain and bulk symmetry factor is proposed to evaluate device sensitivity to asymmetrical characteristics resulting from process parameters. With the use of a simple test structure and a few specific measurements, it allows comparison of the effects of different processes and provides a good predictive tool in terms of aging behavior. It also shows that it is necessary to do a statistical analysis to compare the influences of various processes.

A new technique of plasma nitriding oxide has been developed for very thin gate insulators. The interfacial properties are preserved after plasma nitridation in ammonia at 950°C. Excellent behaviour is observed during aging experiments on transistors using nitrided oxide as the dielectric gate ; the absence of defects due to the plasma as illustrated by the yield achieved for SRAM memories suggests the process compatibility with production.

Statistical analysis of asymmetry in LDD NMOSFETs electrical characteristics shows the influence of implantation angles on non-overlap variation observed on devices realized on a 100 mm wafer and within the wafers of a batch. The study of the consequence of this dispersion on the aging behaviour illustrates the importance of this parameter for reliability and the necessity to take it in account for accurate analysis of stress results.

Hot carrier stressing has been carried out on LDD n-MOS transistors with gate overlap asymmetry, under conditions of strong source field (Vg > Vd). It is shown that, under these conditions, the device actually suffers hot carrier stressing at the source end of the transistor resulting directly from this high source field.