Hot carrier stressing has been carried out on LDD n-MOS transistors with gate overlap asymmetry, under conditions of strong source field (Vg > Vd). It is shown that, under these conditions, the device actually suffers hot carrier stressing at the source end of the transistor resulting directly from this high source field.

Low-temperature MOS devices (77 K) present significant gain in speed and density for a low technological cost. An N-MOS process has been adapted for use at liquid-nitrogen temperature using argon-implanted polysilicon resistors of very small dimensions as loads, instead of depleted devices. A ripple-carry 3-bit adder has been designed with 3- and 2.4-/spl mu/m roles to estimate the speed-power pos...

Low temperature MOS devices (77K) present significant gain in speed and density for a low technological cost. We report results concerning a three bits adder fabricated with an adapted cryogenic N-MOS process, using Argon-implanted polysilicon loads; the maximum measured frequency was 405 MHz for a 28 mW power consumption, with 2.4¿ design rules.