Pour une publication sur Épisciences. Dark Emu (2014), a book written by Bruce Pascoe, argues for a drastic revision of the vision of Aboriginal peoples at the time of the colonisation of Australia. Traditionally presented as nomadic hunter-gatherers, they were in fact for the most part villagers who applied some forms of agriculture and fish farming, all of which were concealed by those who wanted to appropriate their lands, thus forging a false version perpetuated by anthropological tradition. This provocative thesis has had a huge impact in Australia, where it has been the subject of much controversy. Peter Sutton and Keryn Walshe’s book is the first rebuttal by academic specialists–who are also deeply involved in the defence of the rights of Aboriginal communities. Le livre Dark Emu (2014), écrit par Bruce Pascoe, plaide pour une révision drastique de la vision des peuples aborigènes au moment de la colonisation de l’Australie. Traditionnellement présentés comme des chasseurs-cueilleurs nomades, ceux-ci auraient en réalité été pour une bonne part des villageois pratiquant certaines formes d’agriculture et de pisciculture, autant d’éléments dissimulés par ceux qui voulaient s’approprier leurs terres, forgeant ainsi une version mensongère perpétuée par la tradition anthropologique. Cette thèse provocatrice a connu un immense retentissement en Australie, où elle a suscité de très âpres polémiques. Le livre de Peter Sutton et Keryn Walshe en constitue la première réfutation émanant de spécialistes académiques – par ailleurs, profondément impliqués dans la défense des droits des communautés aborigènes.

In this paper, we describe how the IBM z14 processor, together with Db2 for z/OS Version 12, can improve data compression rates and thus reduce data storage requirements and cost for large databases. The new processor improves on the compression hardware accelerator available in earlier IBM Z generations by adding new hardware algorithms that increase the compression ratio and extend the applicability to additional data structures in Db2 for z/OS databases. A new entropy coding step employed after Ziv-Lempel compression reduces the size of data compressed with the prior algorithms by 30% on average. Moreover, the new order-preserving compression algorithm enables database index compression, reducing index sizes by roughly 30%. This results in an overall improvement of 30% of the database size for many applications, with associated benefits in storage requirements, input/output bandwidth, and buffer pool efficiency.

The IBM zEnterprise® Data Compression (zEDC) feature provides integrated high-performance data compression to the IBM z13™ and zEnterprise EC12 and BC12 processors. zEDC is a combined hardware feature (zEDC Express) and z/OS® software solution that provides high-performance, industry-standard-compliant compression and decompression. The zEDC Express device and the z/OS device support have been des...

Flash storage is integrated for the first time on System z® as a card in the EC12 I/O drawer. This provides a number of functions and benefits in the immediate product, in addition to laying a foundation for further system benefits in future generations of System z systems. Enabling flash MLC (multilevel cell) technology as SCM (storage class memory) in an enterprise-class product required myriad diverse individual technological advances, together with a series of system design features. Extreme care and attention were paid to ensure that the required level of System z reliability was maintained. As with legacy I/O, the programming interface is subchannel-based. The subchannel programming interface is expanded with new architecture via the extended asynchronous-data-move facility. Operating system changes were required to enable exploitation of the features that this new system technology offers. These individual hardware, firmware, and software design aspects are described in this paper, along with the overall functionality and system-level value of this new technology.

In this paper we present a simulation framework for rapid testing of custom hardware peripherals designed to be incorporated in a System on Chip (SoC) architecture. The QEMU processor emulator is extended to allow attaching a simulation environment to the system bus, such that simulation can perform bus transactions, and interact with the emulated processor. We demonstrate multiple levels of simulation fidelity with custom hardware simulation ranging from fast functionally equivalent C models through to Hardware In The Loop (HIL) co-simulation of production ready HDL code.

Embedded systems are increasingly moving from running single applications to running application sets. Targeted configurable caches extend the concept of configurable caches by specially supporting the critical applications of an embedded system. Other configurable caches attempt to be completely generic but a targeted configurable cache can outperform them due to reduced overheads and better partitioning from only supporting the needed configurable options for the critical applications. A comparison between a conventional configurable cache and a targeted configurable cache demonstrates targeted performance improvement to that of a conventional configurable cache.

The IBM System z10™ mainframe provides an architectural framework for 1-MB virtual pages. With the new support provided in z/OS® 1.9, these large pages can be transparently used by middleware and applications. The use of large virtual memory pages for storage allocated at addresses above 2 GB can deliver significant performance gains. This paper reviews computer architecture trends and describes various implementations of large pages across the industry to explain why large pages are needed in today's operating system environments. It also reports results from innovative work focused on which workloads are subject to the largest performance boost from the use of large pages and how large-page support has been implemented on the System z10 platform and in the z/OS operating system. Results from recent performance tests are presented and analyzed.

This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.

Existing high-level hardware synthesis tools typically focus on the automated discovery of opportunities for Instruction Level Parallelism (ILP) or alternatively allow designers to explicitly specify instances or opportunities for ILP. We present a novel profiling driven approach to the automated discovery of higher level speculative parallelism opportunities for custom-hardware implementations. The synthesis approach proposed here is to use the customisation capabilities of reconfigurable platforms to implement application specific speculative devices that capitalise on thread and loop level parallelism opportunities that occur with low (or zero) frequency data dependencies. In this paper our program profiling and partitioning techniques are detailed and analysis results are used to generate promising theoretical limits on speedups achievable through thread level parallelism. Such speedups are orthogonal to the gains achievable using existing ILP based optimisations. Our analysis and profiling tools are implemented within the Low Level Virtual Machine (LLVM) compiler infrastructure and results are generated from the SPEC2000INT benchmark suite.

A hierarchy of FPGAs, DSPs, and a multiprocessing microprocessor provide a layered high performance computing module which will be used to enhance the performance of a low-earth orbit satellite, FedSat-1, which will be operational in 2001. The high performance computer will provide additional hardware redundancy, on-board data processing, data filtering and data compression for science data, as well as allowing experiments in dynamic reconfigurability of satellite computing hardware in space.

Infrastructureless networks are becoming more popular with the increased prevalence of wireless networking technology. A significant challenge faced by these infrastructureless networks is that of providing security. In this paper we examine the issue of authentication, a fundamental component of most security approaches, and show how it can be performed despite an absence of trusted infrastructure and limited or no existing trust relationship between network nodes. Our approach enables nodes to authenticate using a combination of contextual information, harvested from the environment, and traditional authentication factors (such as public key cryptography). Underlying our solution is a generic threshold signature scheme that enables distributed generation of digital certificates.

This paper presents a DES/3DES core that will support cipher block chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.

Significant problems have inhibited the wide adoption of reconfigurable computing, including the difficulty of pro- gramming them, and the difficulty of interfacing proces- sor cores to external devices and memory. This paper proposes a strategy for dealing with the external interface problem, starting from a reconfigurable memory system design. The memory system design is based on I/O prin- ciples and could therefore become the basis for an I/O interconnect.