In the early design phase of embedded systems, discrete-event simulation is extensively used to analyse time properties of hardware-software architectures. Improvement of simulation efficiency has become imperative for tackling the ever increasing complexity of multi-processor execution platforms. The fundamental limitation of current discrete-event simulators lies in the time-consuming context switching required in simulation of concurrent processes. In this paper, we present a new simulation approach that reduces the number of events managed by a simulator while preserving timing accuracy of hardware-software architecture models. The proposed simulation approach abstracts the simulated processes by an equivalent executable model which computes the synchronization instants with no involvement of the simulation kernel. To consider concurrent accesses to platform shared resources, a correction technique that adjusts the computed synchronization instants is proposed as well. The proposed simulation approach was experimentally validated with an industrial modeling and simulation framework and we estimated the potential benefits through various case studies. Compared to traditional lock-step simulation approaches, the proposed approach enables significant simulation speed-up with no loss of timing accuracy. A simulation speed-up by a factor of 14.5 was achieved with no loss of timing accuracy through experimentation with a system model made of 20 functions, two processors and shared communication resources. Application of the proposed approach to simulation of a communication receiver model led to a simulation speed-up by a factor of 4 with no loss of timing accuracy. The proposed simulation approach has potential to support automatic generation of efficient system models.

A motion planning algorithm aims to calculate one obstacle-free trajectory which meets the dynamical constraints of a vehicle and leads the vehicle from the start state to the target state. RRT∗ (RRT star) is one sampling-based algorithm which is widely used in many applications because of its speed in quickly finding a trajectory. In contrast with basic RRT (Rapidly-exploring Random Trees) algorithm, RRT∗ improves trajectory optimality significantly by introducing the refinement step after setting up each tree node. This paper describes a new parallel version of the RRT∗ algorithm and its corresponding architecture on an FPGA (Field Programmable Gate Arrays). The refinement step is extracted and runs as a parallel process alongside a continuous tree-extending process. In order to avoid traversing all nodes in every iteration, tree nodes are stored in separate memory blocks and each block is assigned its own tree extending and refining pipelines to enhance the memory throughput. In the experimental evaluation, we take a 3-dimensional state spaces and implement the proposed architecture. The hardware implementation gives a 90 times speed improvement compared with an embedded software implementation, and a 30 times speedup compared to a desktop software implementation.

Random sampling based path planning algorithms have shown their high efficiency in robotics, navigation and related fields. The Rapidly-Exploring Random Trees (RRT) is the typical method and works well in a variety of applications. Due to the sub-optimal issue of original RRT, the recent algorithm, known as RRT*, significantly improves the optimality of solution by adding the “cost review” procedure. However, the original RRT experiences the bottle neck of complicated iterations and it becomes worse in RRT*. This paper presents the developed hardware architecture for RRT*, which fully exploits the parallel potential of algorithm. Unlike the sequential execution in software, the “exploration” and “review” are identified as independent processes and executed in parallel. For the complicated operation of inserting vertexes, one pipelined Kd-tree constructor is designed to fast rebuild the tree when new vertex generated. Furthermore, to speed up the near neighbors and nearest neighbor searching, the vertexes are stored in separate Kd-trees so that the search processes can be carried out concurrently in each data tree. This work explores the possible and power-efficient RRT* hardware architecture on FPGAs compared to PC implementation.

Small unmanned aerial vehicles called micro-UAVs are excellent examples of cyber-physical systems which interact with complex and dynamic environments. The success of this technology depends on smart avionics systems compensating for the physical limitations of small airframes, which have very limited on-board power. This paper presents development of micro-UAV for surveillance of open-cut mining sites that represent significant challenges due to difficult terrain and changing wind conditions. The real time aircraft control is integrated with motion planning based on Rapid-exploring Random Tree (RRT) methods which allow efficient handling of the wind factor. The main computational difficulty with RRT in real time motion planning is overcome by employing reduced forward model (RFM) of the aircraft. We also outline some strategies on integrating motion planning, control, and payload processors in reconfigurable hardware to optimise performance and power consumption. The micro-UAV development process is incremental and in large part based on simulations with hardware in the loop but gathering data from experimental flights is essential for accurate reduced forward models. We developed the avionics and experimental vehicle and used it in surveillance missions over mining sites to validate our approach.

Avionics systems of micro aerial vehicles (MAV) pose unique problems in system design, sensor signal handling and control. This is evident in micro-rotary aircraft as their whole body rotates with the sensors of the flight control. The precise calculation of attitude and heading from magnetometer readings is complex due to the body rotation. It is made even more difficult by noise induced in the geomagnetic signal by fluctuating magnetic field of the closely positioned motors. Filtering that noise is challenging since the rotation speed of motors and the vehicle can be very close. This paper presents analysis of motor induced noise, based on experimental data of brushless micro motors. A novel time domain filter is proposed, designed, implemented in FPGA hardware, tested and compared to other filters. This filter provides good performance even when the rotational rate of the motor and vehicle are close and traditional frequency domain filters would perform poorly.

This paper presents a prototype indoor navigation system for the blind based on wireless sensor network coupled with a haptic feedback glove. The system uses Received Signal Strength Indicator (RSSI) to continuously triangulate the position of the Vision Impaired (VI) person. A number of most relevant destinations can be assigned to pushbuttons on a haptic glove. Upon receiving input from the user via a pushbutton indicating the desired destination a path is routed. To aid in traversing to the destination the individual wears the haptic feedback glove embedded with vibrational motors and an ultrasonic sensor to gauge distance of nearby objects.

Computational methods have become an important part of gene delivery research, as they allow researchers to experiment with different models of cellular processes. Models of the gene delivery process based on telecommunication theory make this experimentation especially efficient. Therefore, this paper presents a specialised FPGA-accelerated heterogeneous architecture for simulating the gene delivery process using queuing theory. We also present an implementation of a programmable M/M/∞ queue simulator, and compare its performance to that of an equivalent software simulator. We finally discuss limitations of our system and outline future work aimed at further performance improvement.

Mobile localisation has numerous uses for logistics, health, sport and social networking applications. Current wireless localisation systems typically require the use of tracking devices to be worn or implanted. The use of tracking devices can hinder the types applications that can be used. Wireless localisation use wireless channel propagation characteristics, such as RF receive signal strength to localise a user's position, which requires the use of complex radio hardware. We developed a wireless tracking system using radio tomographic imaging to track people without wearing a mobile tracking device. We evaluated our wireless localisation network with users in an indoor environment. Our localisation network used the 6LoWPAN wireless communications protocol.

The Rapidly-Exploring Random Trees (RRT) method has been proved successful and efficient for solving path planning problems. Most recent work focuses on optimizing RRT itself and presents the results achieved from software. In this paper a dedicated hardware architecture for FPGA implementation of Rapidly-Exploring Random Tree (RRT) path planning is developed. The proposed architecture fully takes advantage of FPGAs' natural parallel computing ability. The near neighbour (NN) search speed is improved by splitting the whole search space into several sub-spaces; correspondingly the tree nodes are stored in separate block RAMs and each Block RAM owns its independent traversal query module to enhance the memory throughput. Furthermore, to speed up the space exploration, each single path planning unit consists of two cooperating RRT modules which grow trees from each end of the path. One complete path planner involves several path planning units which work in a parallel master-slave mode to increase the probability of obtaining available path. Implementation in a 2D environment shows good path planning performance of the hardware design, with a 30x speed improvement compared to a PC implementation.

Micro-UAVs (Unmanned Aerial Vehicles) attract much interest in a wide range of commercial applications. Due to small size, very limited power and susceptibility to wind their design poses difficult problems in control and motion planning. FPGA technology allows integration of high speed control circuits with efficient hardware implementations of complex algorithms on the same reconfigurable hardware chip. This is a very attractive option for implementation of a micro-UAV computing platform. This paper presents development of control platform for micro-UAVs focusing on integration of lower level control with online motion planning in wind. Some aspects of tight integration of on-board optical sensors with the aircraft control system are also discussed.

Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models.

Easy, available and inexpensive modules like digital radio or modems and sensors allow the practical understanding of communication technology. We present a Commercial off the Shelf (COTS) Internet platform for teaching digital and wireless communications. Our experience showed that teaching embedded systems by building a realistic system is most convincing for students as it shows theory applied and engages students better then a more theoretical approach. We created an Internet platform development environment and a Blimp UAV that introduced wireless and digital communication systems, realtime OS and embedded networking concepts.

The ability of UAV's (Unmanned Aerial Vehicles) to land on unknown and uneven terrain is an important area of research, particularly for applications such as field surveillance. This paper presents a novel solution to this problem using mechanical design, with a legged landing gear design that provides both suspension and stability on uneven terrain. The key features of this design are differential loading across legs as well as a conditional locking mechanism that resists post-landing disturbances. Results from a prototype design show robust stability when landing on uneven surfaces inclined up to 20 degrees, with analysis of an optimally damped suspension profile (for an approximated mass spring damper system with constant damping).

In order to reduce redesign iterations occurring in the design of analog integrated circuits, it is desirable to estimate layout-induced parasitics during the circuit synthesis phase. Since parameterized layouts allow us to build models of parasitics automatically and systematically, researchers have proposed to use them in an analog design flow so as to estimate parasitics during the circuit synthesis phase. In this paper, we propose methods for designing and representing the parameterized layout of a two-turn octagonal spiral inductor. The parameterized layout contains a parameterized 45-degree polygon. Also, the parameterized layout is process-independent and can be used to generate design-rule-correct physical layouts for given inductance values. The proposed methods are general and can be applied to the design and representation of parameterized layouts for other basic building blocks in analog integrated circuits.

The Infopoint Explorer is an outdoor personal area network for location-based services that allows users to access locality information interactively using mobile computing devices such as PDAs and smartphones. The Infopoint explorer was used to study the limitations imposed by inexpensive and popular wireless technologies such as Bluetooth for outdoor location-based services. The Infopoint Explorer functioned as a multimedia guidebook that allowed access to location-specific information using wireless Infopoints. The Infopoints detect and attempt to transfer multimedia content to nearby mobile computing devices using Bluetooth connectivity. An adaptive Bluetooth Inquiry Access Code algorithm was developed to reduce the time taken for the Infopoint to detect nearby devices. The Infopoint was powered with solar panels and was deployed for a four-month trial. During the trial, over 8,000 Bluetooth connections were attempted, with 300 successful transfers.

In this paper, an approach to the partitioning of parameterized 45-degree polygons into parameterized trapezoids by using horizontal cuts is proposed. In the process of partitioning a parameterized 45-degree polygon, the proposed approach invokes a mixed integer linear programming solver only once and can rapidly obtain results of comparing linear expressions. Compared with previous partitioning programs, the program implementing the proposed approach is very efficient and can achieve more than 100× speed-up while partitioning large parameterized polygons or parameterized polygons with complex constraints. The approach can be used as the basis to build trapezoidal corner stitching data structures for parameterized 45-degree layouts so that models of layout-induced parasitics can be generated automatically.

Since analog circuits are usually very sensitive, it is desirable to consider layout-induced parasitic effects early in a design flow. In a proposed layout-aware analog design methodology based on the use of parameterized 45-degree layouts, parasitics can be estimated in the circuit synthesis phase if models of extracted circuits can be generated from these layouts. In order to perform circuit extraction from parameterized 45-degree layouts, algorithms are required for dealing with parameterized 45-degree polygons and relevant constraints. In particular, algorithms for performing Boolean mask operations on parameterized 45-degree polygons are essential in the circuit extraction process. In this paper, an efficient approach is proposed for performing Boolean mask operations on parameterized 45-degree polygons. To the best of our knowledge, this paper is the first in the literature to present an approach for performing these operations.