This paper presents the design and experimental characterization of a high-power monolithic SOI-CMOS Front End-Module (FEM) supporting Wi-Fi 6 signals over the 5.1 to 5.9GHz frequency band. The FEM includes an SP3T antenna switch, a power amplifier (PA), a low noise amplifier (LNA) with bypass mode, and a digital controller. The LNA achieves 14dB of power gain with less than 2.1dB of noise figure (NF) with 25mW of power consumption. The reconfigurable differential Class-J PA delivers 32dBm of saturated output power (P-sat) with 34% of peak PAE. Without DPD, the reconfigurable PA achieves state-of-the art performance with 20/18dBm of linear output power (P-out) for an EVM of -34/-37.5dB with 80MHz MCS9/MCS11 signals.

In this paper, a novel scalable transformer-based output matching network (OMN) for differential Class-E power amplifier (PA) is developed and used to elaborate a comprehensive design methodology that maximizes the operating bandwidth. The proposed methodology is used to design a wideband fully-integrated WiFi-6 PA, in 130 nm SOICMOS process, achieving more than 27.8 dBm of saturated output power ($\mathbf{P}_{\text {sat }}$) with $\mathbf{3 2 - 3 9. 5 \%}$ of peak PAE over the $\mathbf{5. 1}$ to 6.6 GHz frequency band. The proposed $P A$ achieves state-of-theart performance with higher than 18.7 dBm of linear output power with -42 dB of EVM using $80 \text{MHz} 1024-{}$ QAM WiFi-6 signal from 5.1 to 6.6 GHz.

This paper presents the design and experimental characterization of a compact two-stage monolithic microwave integrated circuit (MMIC) power amplifier (PA) implemented in a 150nm GaN/SiC high electron mobility (HEMT) technology. The proposed PA achieves 31.2-31.9dBm of saturated output power (P-sat), 36.7-39.2% peak PAE and a small-signal gain of 18.6-20.5dB across the n258 (24.25-27.5GHz) band, under CW excitation. The PA exhibits high linearity under 100/400MHz 5G QPSK downlink signals and achieves -24.5/-25.1dBc ACLR, 24.8/24.5dB EVM, for an average P-out of 24.2/20dBm and PAE of 22.1/11%, at 26GHz without digital pre-distortion (DPD). Its compact size (2mm(2)) and high performance advance the state-of-the-art (SOTA) for GaN MMIC PAs operating in the 5G n258 (24.25-27.5GHz) frequency band.

This papers proposes a novel design methodology to enhance bandwidth (BW) and efficiency in single-input Sequential Load Modulated Balanced Amplifier (S-LMBA). It investigates the impact of lossy off-state impedance of the auxiliary devices on efficiency degradation at back-off (BO) power and discusses the optimum choice of the auxiliary stage’s output matching network to minimize this impact. Additionally, a practical approach to extract the optimum main-to-auxiliary phase shift profile that maximizes bandwidth and efficiency is proposed. The proposed methodology is experimentally validated through the design and measurement of a 43dBm S-LMBA prototype. Between 3-4.2 GHz, the measured prototype achieves 42.1-43.5 dBm of P sat , a drain efficiency (DE) of 56.5%-66% and 45%-53% at peak and 9-dB BO, respectively.

Mobile and WiFi applications are stimulating ma or research efforts on next-generation power amplifiers (PAs) in order to get improved linearity and operating bandwidth with reduced power consumption. The need is for a higher integration push for the development of compact integrated PAs capable of supporting an ever-increasing number of frequency bands with high linear output power. Today, CMOS SOI technology appears as an attractive choice for efficient PA integration. This paper presents a comprehensive overview of recent CMOS SOI PA solutions targeting high-performance mobile and WiFi applications.

In this brief, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at −35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively.

This work presents a SOI-LDMOS Dual-Input Doherty Power Amplifier (DPA). The proposed DPA is implemented in a 130nm SOI-CMOS technology and packaged using flip-chip on a laminate substrate. Low DPA combiner loss is achieved using high-Q inductors embedded onto the laminate. The proposed Doherty PA exhibits a measured peak output power of 30 dBm at 3.2GHz, under 3.4V voltage supply. The peak Power-Added Efficiency (PAE) is 40%, and PAE at 27dBm output power is 37%. With a 10MHz LTE signal, the linearized DPA achieves a measured ACLR of -42 dBc at 27dBm output power.