This paper presents the design and experimental characterization of a high-power monolithic SOI-CMOS Front End-Module (FEM) supporting Wi-Fi 6 signals over the 5.1 to 5.9GHz frequency band. The FEM includes an SP3T antenna switch, a power amplifier (PA), a low noise amplifier (LNA) with bypass mode, and a digital controller. The LNA achieves 14dB of power gain with less than 2.1dB of noise figure (NF) with 25mW of power consumption. The reconfigurable differential Class-J PA delivers 32dBm of saturated output power (P-sat) with 34% of peak PAE. Without DPD, the reconfigurable PA achieves state-of-the art performance with 20/18dBm of linear output power (P-out) for an EVM of -34/-37.5dB with 80MHz MCS9/MCS11 signals.

In this paper, a novel scalable transformer-based output matching network (OMN) for differential Class-E power amplifier (PA) is developed and used to elaborate a comprehensive design methodology that maximizes the operating bandwidth. The proposed methodology is used to design a wideband fully-integrated WiFi-6 PA, in 130 nm SOICMOS process, achieving more than 27.8 dBm of saturated output power ($\mathbf{P}_{\text {sat }}$) with $\mathbf{3 2 - 3 9. 5 \%}$ of peak PAE over the $\mathbf{5. 1}$ to 6.6 GHz frequency band. The proposed $P A$ achieves state-of-theart performance with higher than 18.7 dBm of linear output power with -42 dB of EVM using $80 \text{MHz} 1024-{}$ QAM WiFi-6 signal from 5.1 to 6.6 GHz.

This paper proposes a novel design methodology combining class-E power amplifiers (PAs) with Sequential Load Modulated Balanced Amplifier (S-LMBA) architecture to enhance its bandwidth and efficiency. The proposed methodology aims to align the frequency-dependent optimal impedance trajectory of class-E PAs with the frequency-dependent optimal impedance trajectory of the S-LMBA's auxiliary stage, thereby expanding the achievable bandwidth of the S-LMBA architecture. The proposed methodology is validated on a PCB design using commercial GaN HEMT devices. The fabricated class-E S-LMBA achieves 41.9-43.4dBm output power with 56-70% Drain efficiency (DE) at saturation and 34-49% of DE at 9-dB output power back-off (OBO) from 2.9 GHz to 4.2 GHz.

This paper presents the design and experimental characterization of a compact two-stage monolithic microwave integrated circuit (MMIC) power amplifier (PA) implemented in a 150nm GaN/SiC high electron mobility (HEMT) technology. The proposed PA achieves 31.2-31.9dBm of saturated output power (P-sat), 36.7-39.2% peak PAE and a small-signal gain of 18.6-20.5dB across the n258 (24.25-27.5GHz) band, under CW excitation. The PA exhibits high linearity under 100/400MHz 5G QPSK downlink signals and achieves -24.5/-25.1dBc ACLR, 24.8/24.5dB EVM, for an average P-out of 24.2/20dBm and PAE of 22.1/11%, at 26GHz without digital pre-distortion (DPD). Its compact size (2mm(2)) and high performance advance the state-of-the-art (SOTA) for GaN MMIC PAs operating in the 5G n258 (24.25-27.5GHz) frequency band.

This papers proposes a novel design methodology to enhance bandwidth (BW) and efficiency in single-input Sequential Load Modulated Balanced Amplifier (S-LMBA). It investigates the impact of lossy off-state impedance of the auxiliary devices on efficiency degradation at back-off (BO) power and discusses the optimum choice of the auxiliary stage’s output matching network to minimize this impact. Additionally, a practical approach to extract the optimum main-to-auxiliary phase shift profile that maximizes bandwidth and efficiency is proposed. The proposed methodology is experimentally validated through the design and measurement of a 43dBm S-LMBA prototype. Between 3-4.2 GHz, the measured prototype achieves 42.1-43.5 dBm of P sat , a drain efficiency (DE) of 56.5%-66% and 45%-53% at peak and 9-dB BO, respectively.

This paper extends the quasi-load insensitive (QLI) Class-E Doherty power amplifier (PA) design methodology to address Doherty PA combiners with complex load impedance trajectories. The analysis of the Class-E PA power and efficiency load-pull contours shows that changing the class-E network resonance factor allows rotating the loadpull contours to achieve QLI operation with various Doherty combiners. Moreover, an alternative approach using a modified class-E network is proposed to overcome the frequency limitation that might be caused by the class-E network resonance factor choice. To validate the proposed methodology, a 40 W Doherty PA is designed and simulated using commercial GaN HEMT transistors achieving more than 70% Efficiency over 6-dB output power back-off at 3.8 GHz.

We report on the development of CMOS compatible SiN/AlN/GaN MIS-HEMT process on 200mm Si substrates for Ka-band power amplification. The combination of soft gate process, gate design with reduced electric field, in- situ SiN gate dielectric, low temperature ohmic contacts, low substrate RF losses and GaN:C back-barrier leads to Ft/F MAX of 81/173GHz for 2x50μm devices with L G =150nm. At 28 GHz, the device shows performance similar to other GaN/Si technologies at V DD =10V and competitive performance with GaN/SiC at V DD =20V with PAE=41% and P SAT = 6.6W/mm.

A high voltage N-type Drain Extended MOS (NDEMOS) in 40nm RFSOI technology is presented for PA application. After a careful optimization of the drain extension, the NDEMOS transistor exhibits a f T .BV>700 GHz.V & f MAX =205GHz at L g =70nm & V DD =2V, that meet the PA requirements at mmW frequency. The large-signal RF performance of a common-source NDEMOS PA cell are assessed. It exhibits 19.2dBm of P SAT @V DD =3V, that may be further improved in a cascode configuration. With this NDEMOS device, this 300mm SOIMMW technology becomes a very cost effective platform for Front End modules (FEM) that can be competitive with other CMOS technologies (Fig. 26).

Mobile and WiFi applications are stimulating ma or research efforts on next-generation power amplifiers (PAs) in order to get improved linearity and operating bandwidth with reduced power consumption. The need is for a higher integration push for the development of compact integrated PAs capable of supporting an ever-increasing number of frequency bands with high linear output power. Today, CMOS SOI technology appears as an attractive choice for efficient PA integration. This paper presents a comprehensive overview of recent CMOS SOI PA solutions targeting high-performance mobile and WiFi applications.

A Capacitor Assisting Triple-Winding Transformer Low-Noise Amplifier with

This paper presents a high-power monolithic SOI-CMOS Front End-Module (FEM) supporting Wi-Fi 6/6E signals at 2.4GHz. The FEM includes an SP4T antenna switch, a power amplifier (PA), a low noise amplifier (LNA) with bypass mode, and a digital controller. The RX path achieves 15dB of power gain with less than 1.8dB of noise figure (NF) with 10mW of power consumption. The TX path delivers 33.4dBm of saturated output power $(\mathrm{P}_{\text{sat}})$ with 51.7% of peak PAE and 28.5dB of power gain. Without DPD, the reconfigurable TX path achieves state-of-the art performance with 23.4/20dBm of linear output power $(\mathrm{P}_{\text{out}})$ for an EVM of −35.1/−43.9dB and an operating current of 282/254mA for 802.11ac/ax MCS9/MCS11 40MHz signals.

In this brief, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at −35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively.

This paper presents the first high-power SOI-CMOS power amplifier (PA) embedded in a Fan-Out Wafer Level Package (FOWLP) and addressing 2.4 GHz Wi-Fi 6 applications. At 2.44 GHz, the PA delivers 35.1 dBm of saturated output power (Psat) with 53% of peak PAE and 29.5 dB of power gain. Without DPD, the PA achieves state-of-the art measured performance with 26.5/24.5/21.9 dBm of linear output power (Pout) for an EVM (Error Vector Magnitude) of −30/−35/−43 dB with an operating current of 336/270/210 mA for MCS7/9/11 40MHz signals respectively. The PA shows robust operation under extreme load mismatch (8:1 VSWR) and temperature (-40 to 80°C) conditions.

A reconfigurable broadband Doherty PA module for LTE HPUE (High Power User Equipment) applications is presented, which is the first to be based on an SOI-CMOS PA without predistortion and supply modulation. The PA die (1.3×1.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) is fabricated in a 130nm SOI-CMOS process and assembled, using flip-chip, on a 3.2×3.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> laminate package. From 1.9GHz to 2.7GHz, the PA provides 28dBm of output power (P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</inf> ) under 3.4V supply voltage (Vdd), with a PAE higher than 35% and an E-UTRA ACLR lower than -35dBc when using a 10MHz-50RB QPSK LTE uplink signal, without predistortion. At 2.3GHz, the proposed PA achieves 43.5% of PAE and -39.6dBc of ACLR at 28dBm of P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</inf> . When operating at Vdd=5V (HPUE mode), the PA reaches a saturated power of 4W with a maximum PAE of 57% and delivers a P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</inf> of 31dBm with 42.6% of PAE and -35.7dBc of ACLR using a 20MHz-100RB QPSK LTE signal.

A B BITS Pilani, India Awani Khodkumbhe C Preserving Polar Modulated Class-E Power Amplifier Linearity Under Load Mismatch Brandenburgische Technische Universität, Germany M. Rudolph C W-Band Noise Characterization with Back-Gate Effects for Advanced 22nm FDSOI mm-Wave MOSFETs C Caltech, USA Ali Hajimiri C The Flexible Future of RF CEA-Leti, France R. Berro, B. Blampey, A. Boulmirat, F. Chaix, C. Dehos, A. Giry, J.L. Gonzalez-Jimenez, A. Hamani, Clement Jany, E. Mercier, R. Mourot, D. Parat, M. Pezzin, P. Reynier, A. Serhan, A. Siligaris C A Reconfigurable SOI CMOS Doherty Power Amplifier Module for Broadband LTE High-Power User Equipment Applications C A Multichannel Programmable High Order Frequency Multiplier for Channel Bonding and Full Duplex Transceivers at 60GHz Band Chengdu University, China Benqing Guo C A 0.08mm2 1–6.2GHz Receiver Front-End with Inverter-Based Shunt-Feedback Balun-LNA

5G are stimulating major research efforts on next-generation power amplifiers (PAs). This paper presents a comprehensive overview of recent linear watt-level PA developments for mobile applications operating below 6GHz. A survey on state-of-the-art PAs is presented focusing on recently published envelope tracking and Doherty architectures.

This work presents a SOI-LDMOS Dual-Input Doherty Power Amplifier (DPA). The proposed DPA is implemented in a 130nm SOI-CMOS technology and packaged using flip-chip on a laminate substrate. Low DPA combiner loss is achieved using high-Q inductors embedded onto the laminate. The proposed Doherty PA exhibits a measured peak output power of 30 dBm at 3.2GHz, under 3.4V voltage supply. The peak Power-Added Efficiency (PAE) is 40%, and PAE at 27dBm output power is 37%. With a 10MHz LTE signal, the linearized DPA achieves a measured ACLR of -42 dBc at 27dBm output power.

A novel analytical approach is used to determine a new boundary condition for optimal operation of a class B Chireix outphasing PA. In the proposed method, a threshold outphasing angle is defined as a new design parameter and used to optimize the power stage in an outphasing system.

A robust and low cost Si RFSOI Power Transistor which can deliver +31dBm output power with 74% of Power Added Efficiency (PAE) and 18dB of Gain has been optimized for 4G & 5G sub-6GHz Power Amplifier (PA). By means of innovative characterizations combining RF aging tests and modeling, it is proved that this great performance can be achieved while maintaining a very high level of reliability of the PA transistor.