Many experiments in the physical sciences require high temporal resolution on multiple control channels and can benefit from conditional logic control of the experimental sequence patterns. We present LithPulser, a field programmable gate array (FPGA) based open-source digital pulser solution with 1 ns time resolution on 14 digital output channels. The pulser is set up on the affordable Xilinx Zynq-7010 FPGA in the form of the Red Pitaya STEMlab board 125-10. It offers up to 125 MHz bandwidth and a sequence duration of up to 4.2 s and features 16 sequence play control, including a conditional logic module reactive to input events in real-time. LithPulser is designed for a trial until success experimental use case.

Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.

In asynchronous quasi delay-insensitive (QDI) circuits, temporal masking is a serious concern because of their event-driven behavior, which makes them prone to environmental effects: Data acceptance windows, e.g. are defined by transitions (token/acknowledgement) alone, without temporal bounds, therefore a glitch occurring anytime throughout such a window cannot be distinguished from an expected, correct transition in a straightforward manner and hence threatens data integrity. Therefore, shortening that window is one proposed way in the literature to enhance temporal masking in QDI designs.We examine a variant of the Weak-Conditioned Half Buffer (WCHB) called Interlocking WCHB (which wisely shortens the transition window) because of its glitch filtering properties and a low cost implementation as compared to other variants. We propose modifications that enhance its dealing with illegal token words specifically when waiting for acknowledgment signal transitions in the so-called bubble limited operation mode. A very strict triple-check input filter with a glitch filter preventing the buffer from capturing an illegal state is used, which also enhances the deadlocking rate of the circuitry.

Experimental fault injection is an essential tool in the assessment and verification of fault-tolerance properties. Often, in these experiments it is impossible to reasonably cover the huge parameter space spanned by target state and fault parameters, and compromises or restrictions must be made. This is even more pronounced for asynchronous circuits where a convenient discretization of time through a synchronous clock is not possible. In this paper we present a fault-injection toolset that allows for a very efficient injection and data processing, thus bringing studies with many billions of meaningful injections into asynchronous targets within reach. The key ingredients of our solution are an auto-setup feature capable of optimizing parameter values, seamless distribution of the simulation load to many host computers, and efficient arrangement of the important settings and readings in a database. We will use the example of a comparative study of different asynchronous pipeline styles to motivate the need for such an approach and illustrate its benefits.