Nano-electromechanical switches (NEMS) are a promising chip technology for harsh environments. However, their use with conventional synchronous designs may face hurdles, as wear-out limits their number of switching cycles. In this paper we propose a novel implementation of a Muller C-Element for NEMS devices and present two case studies showing that Quasi Delay Insensitive (QDI) design can significantly decrease the number of switching cycles and thus extend the lifetime of the circuit, potentially even without an increase of the device count. Our results indicate that the benefits of QDI become more pronounced for circuits that have a high proportion of flip-flops, and in cases where slow input causes idle clock cycles. Overall, our approach of using a customized Muller C-Element in a QDI design style shows clear benefits for the considered NEMS technology.

Over the last two decades, Convolutional Neural Networks (CNNs) have become common in a wide variety of tasks, including safety-critical ones such as autonomous driving, leading to optimizations such as Sparse Convolutional Neural Networks (SparseCNNs). Scaling technological nodes has led to an exponential increase in transient faults affecting the systems, generating critical soft errors. We introduce SBanTEM, a novel methodology for employing sparse band tensors as soft-error mitigation in SparseCNNs. SBanTEM includes a novel mitigation technique, employing band tensors, as they do not require using indices for storing data. We employ progressive reduction of the bandwidth of the selected tensors, allowing the network to train in-between successive prunings, and compensate accuracy loss. Additionally, we implement a Genetic Algorithm (GA) to optimally select the tensors bandwidths in the network. We analyze the resilience of many state-of-the-art CNNs on multiple datasets, showing that resilience is much lower for SparseCNNs, and using SBanTEM makes them as resilient as standard CNNs. SBanTEM's code and results is available at github.com/Alexei95/SBanTEM to boost reproducibility and reusability of the implementation.

An important class of attacks is based on manip-ulating the victim's hardware clock to gain control over the system. We propose a circuit that can be added to an IP module to detect and hence mitigate such attacks. It employs a ring oscillator as a tamper-proof internal time reference. We embed this oscillator into a complete circuit whose design carefully takes metastability issues at the boundary between supervised clock and reference clock into account. Furthermore, we analyze the attainable accuracy considering the frequency ratio between these clocks, as well as ring oscillator frequency tolerances. Finally, we give guidelines to parameterize our circuit for given requirements and present a demo implementation as a proof of concept.

Deep Learning (DL) systems have proliferated in many applications, requiring specialized hardware accelerators. An efficient fault-injection methodology is needed for analyzing the resilience of advanced DL systems against different types of faults, which can lead to undetectable and unrecoverable errors. Typically, in a fault injection campaign, the faults are sampled from the random uniform space covering all the possible faults. However, this method is extremely inefficient for large Deep Neural Networks (DNNs), and existing solutions require apriori knowledge on the model, filtering out the search space. Therefore, we propose EISFINN, a novel methodology that employs user-selected neuron sensitivity algorithms to generate importance sampling-based fault-scenarios. Without any a-priori knowledge of the model-under-test, EISFINN provides an equivalent reduction of the search space as existing works, while allowing long simulations to cover all the possible faults, improving on existing model requirements. Our experiments show that the importance sampling provides up to 10x higher precision in selecting critical faults than the random uniform sampling, in less than 100 faults.

The causal behavior of Quasi Delay-Insensitive (QDI) circuits may get compromised under the effects of single event transients (SETs). To address the issue, the research community already made efforts in different directions, like with modular redundancy, or shortening the data accepting windows of buffer templates. Nevertheless, in non-modular techniques, the focus remains towards the buffers and combinational logic. Most of the time the conditional control elements, namely Multiplexer and De-multiplexer, are not explicitly addressed. However, for the event-driven behavior these elements are also realized with a storage element called Muller C-element (MCE), so in principle these elements also require special consideration to improve the overall fault tolerance of the circuit. In this article we first analyze the error contribution of these elements during single event transient (SET) strikes and then present a hardening technique to mitigate these effects. The focus is to utilize the inherent fault-tolerance properties of QDI circuits. For better coverage of scenarios we test our technique with two different target circuits, an 8-bit Arithmetic Logic Unit (ALU) circuit designed in a simple linear fashion and a 16-bit iterative multiplier. The analysis includes the state-of-the-art buffer template with one of its SET hardened derivatives named Delta. The findings suggest 40% improvement in tolerance towards SETs with Delta_E, our proposed template with resilient conditional control elements.

The IEC 61499 standard facilitates the deployment of flexible decentralized control architectures. Current IEC 61499 runtime systems nearly exclusively focus on synchronous software solutions. Although synchronous FPGA-implemented Function Blocks provide a speed-up, a single clock domain, which has been used so far, lowers the flexibility of individual Function Blocks. The event-based communication layout in the standard seems to lend itself rather to an asynchronous implementation. Consequently, this paper proposes an FPGA implementation in which the Function Blocks are internally still comprised of a (locally) synchronous state machine, while their communication follows asynchronous principles. We explore the feasibility of that approach by designing a comprehensive generic communication infrastructure and, on top of that, implementing a case study exhibiting randomized input variables and different clock and input frequencies in an FPGA. Based on this implementation, we explore the bottlenecks of our approach and elaborate potential improvements.

Due to their unbounded data accepting windows asynchronous circuits seem to be more susceptible to environmental effects than their synchronous counterparts with their strict data latching protocol. The technology advancement makes single event transients (SETs) more of a concern towards reliable operation.To better understand the properties of the mentioned classes we present their behaviour under the influence of SETs in a more detailed view that helps to visualize their unseen characteristics. For comparison we propose a way of fault injection where the length of a fault pulse is not fixed, calculated based on maximum gate delay, but related to the circuit's computation steps instead.The analysis concludes that asynchronous quasi delay-insensitive (QDI) circuits show better resilience against SETs due to two main reasons: (1) if realized with a 4-phase handshake protocol they are 95 to 97% resilient to negative fault pulses (2) the susceptibility of a circuit is largely unchanged for increasing fault length because of the causality underlying the QDI principle.Our analysis provides insights leading towards more resilient QDI circuits: if we only make a circuit or specific gates better resist "1" faults, we are fully resilient towards the single event transient (SET)s because "0" faults are already filtered out by its inherent behaviour. This is also beneficial for area efficiency; as asynchronous circuits often require already double or more area and computation time compared to synchronous circuits, adding extra SET mitigation with double-up or other buffer redundant techniques tends to result in painful overheads. Being able to focus the protection to "1" faults, as indicated by our analysis, can hence yield important savings.

Dynamic partial reconfiguration enables multi-tenancy in cloud-based FPGAs, which presents security challenges for tenants, IPs, and data. Malicious users can exploit FPGAs for remote side-channel attacks (SCAs), and shared on-chip resources can be used for attacks. Logical separation can ensure design integrity, but on-chip resources can still be exploited. Conventional SCA mitigation can help, but it requires significant effort, and bitstream checking techniques are not highly accurate. An active on-chip defense mechanism is needed for tenant confidentiality. Toward this, we propose a lightweight shielding technique utilizing ring oscillators (ROs) to protect applications against remote power SCA. Unlike existing RO-based approaches, in our methodology, an offline pre-processing stage is proposed to carefully configure power monitors and an obfuscating circuit concerning the resource constraints of the board. Detection of power fluctuations due to application execution enables the obfuscating circuit to flatten the power consumption trace. To evaluate the effectiveness of the proposed SHIELD, we implemented it on a Xilinx Zynq-7000 FPGA board executing an RSA encryption algorithm. Due to the SHIELD, the number of traces required to extract the encryption key is increased by 166x, making an attack extremely hard at run-time. Note that the proposed SHIELD does not require any modification in the target application. Our methodology also shows up to 54% less power consumption and up to 26% less area overhead than the state-of-the-art random noise-addition-based defense.

For clock and data transitions in close temporal proximity, synchronous memory elements potentially enter metastability, which leads to unintended output behavior. Although respective analyses in literature have already derived suitable explanations, almost all of them modeled the control (clock) signal transition with negligible rise/fall time. In modern circuits this assumption is, however, not reasonable any more. In fact, due to a finite slope, intermediate clock signal values have to be considered during a large share of the storage process, while their concrete impact is not yet sufficiently explored. In this paper we thus use static and dynamic considerations to thoroughly investigate the behavior of a latch for arbitrary analog control, data and output values, i.e., during the storage process. Basic circuit considerations allow us to derive a unified model which identifies the latch as a Schmitt Trigger with vastly varying hysteresis. We verify the correctness of our predictions by comparison to analog SPICE simulations. Finally we are able to generalize our findings and thus provide explanations for yet unexplained behavior reported in literature.

Due to their flexible data accepting windows Quasi Delay-Insensitive (QDI) circuits are susceptible to environmental effects such as single event transients (SETs). Their mode of operation often demands that the combinational logic of such circuits contains storage elements in the form of Muller C-element (MCE)s. This fact makes it likely for an SETs to be converted into an single event upset (SEU). Nevertheless, most of the available approaches in literature focus on hardening the butter elements between combinational logic blocks to mitigate the effects of SETs with less emphasis on the logic itself. In this work, we first review existing techniques addressing SETs in combinational logic. We analyze and compare them to a non-resilient basic QDI circuit template. We conclude that these techniques are not effective compared to this basic template because the addition of extra circuitry increases the susceptibility of the overall circuit towards SETs. Some of these techniques are only valid with extra assumptions, one is, exempting the mitigating circuit part from fault injection. Another main limitation is concerning the way in which the circuits flush out faults in the combinational logic. The proposed techniques can easily lead to a violation of the handshake protocol by forcing all combinational signals to zero, which may introduce an additional null phase depending on the next stage. After thorough analysis, we present a technique to flush the erroneous value within the combinational logic while maintaining the remaining part of combinational logic. This flushing does not require extra combinational cycles for re-computing the logic value. We combine our novel flushing approach with a resilient butter style to make the overall circuits highly resilient towards SETs. To facilitate a fair comparison we also utilize this resilient butter template with other combinational logic flushing techniques. For the evaluation of the results, we simulate all techniques with a 16-bit multiplier circuit realized with the NanGate 15nm library. The extensive fault injection experiments show the resilience of our novel combinational logic flushing approach.

Deep Learning (DL) systems have proliferated in many applications, requiring specialized hardware accelerators and chips. In the nano-era, devices have become increasingly more susceptible to permanent and transient faults. Therefore, we need an efficient methodology for analyzing the resilience of advanced DL systems against such faults, and understand how the faults in neural accelerator chips manifest as errors at the DL application level, where faults can lead to undetectable and unrecoverable errors. Using fault injection, we can perform resilience investigations of the DL system by modifying neuron weights and outputs at the software-level, as if the hardware had been affected by a transient fault. Existing fault models reduce the search space, allowing faster analysis, but requiring a-priori knowledge on the model, and not allowing further analysis of the filtered-out search space. Therefore, we propose ISimDL, a novel methodology that employs neuron sensitivity to generate importance sampling-based fault-scenarios. Without any a-priori knowledge of the model-under-test, ISimDL provides an equivalent reduction of the search space as existing works, while allowing long simulations to cover all the possible faults, improving on existing model requirements. Our experiments show that the importance sampling provides up to 15x higher precision in selecting critical faults than the random uniform sampling, reaching such precision in less than 100 faults. Additionally, we showcase another practical use-case for importance sampling for reliable DNN design, namely Fault Aware Training (FAT). By using ISimDL to select the faults leading to errors, we can insert the faults during the DNN training process to harden the DNN against such faults. Using importance sampling in FAT reduces the overhead required for finding faults that lead to a predetermined drop in accuracy by more than 12x.

Schmitt-Triggers (S/Ts) are often utilized to clean noisy analog signals at intermediate voltage values in digital circuits. However, they are vulnerable to metastability, which may cause the same undesired non-digital output behavior that was supposed to be removed in the first place. To enable an efficient characterization of static and dynamic metastability properties of S/Ts (e.g., the metastable voltages, the resolution time constants and the overall total resolution times), this work introduces multiple simulation approaches based on control theory, AC, DC and transient analyses. The accuracy and runtime of all methods are compared and discussed by applying them to an analytically describable idealized circuit model as well as three common circuit implementations. Altogether, this work represents a comprehensive resource for investigating the metastable behavior in S/Ts. Even more, the proposed methods are applicable beyond the S/T, enabling an efficient characterization of static and dynamic metastable behavior in general circuits as well.

Research on Deep Neural Networks (DNNs) has focused on improving performance and accuracy for real-world deployments, leading to new models, such as Spiking Neural Networks (SNNs), and optimization techniques, e.g., quantization and pruning for compressed networks. However, the deployment of these innovative models and optimization techniques introduces possible reliability issues, which is a pillar for DNNs to be widely used in safety-critical applications, e.g., autonomous driving. Moreover, scaling technology nodes have the associated risk of multiple faults happening at the same time, a possibility not addressed in state-of-the-art resiliency analyses. Towards better reliability analysis for DNNs, we present enpheeph, a Fault Injection Framework for Spiking and Compressed DNNs. The enpheeph framework enables optimized execution on specialized hardware devices, e.g., GPUs, while providing complete customizability to investigate different fault models, emulating various reliability constraints and use-cases. Hence, the faults can be executed on SNNs as well as compressed networks with minimal-to-none modifications to the underlying code, a feat that is not achievable by other state-of-the-art tools. To evaluate our enpheeph framework, we analyze the resiliency of different DNN and SNN models, with different compression techniques. By injecting a random and increasing number of faults, we show that DNNs can show a reduction in accuracy with a fault rate as low as $7\times 10^{-7}$ faults per parameter, with an accuracy drop higher than 40%. Run-time overhead when executing enpheeph is less than 20% of the baseline execution time when executing 100 000 faults concurrently, at least 10× lower than state-of-the-art frameworks, making enpheeph future-proof for complex fault injection scenarios. We release the source code of our enpheeph framework under an open-source license at https://github.com/Alexei95/enpheeph.

Bluetooth (BT) has revolutionized close-range communication enabling smart capabilities in everyday devices through wireless technology. One of the most important sub-domains of Internet-of-Things (IoT) specializes in the usage of BT technologies to develop smart homes and environments, which include hospitals, buildings, shopping facilities, etc. to offer a wide-range of features, like instantaneous and remote access to ventilation, lighting, security, localization, and tracking. However, the deployment of such features in smart infrastructures are typically unaccompanied by appropriate security measures that safeguard the data and protect its users. Towards this, we propose the ATLAS framework, which is composed of our novel IoT architecture and secure networking stack that can be used to anonymously localize and track smartphones and wearables by deploying multiple Bluetooth Low Energy (BLE) beacons across the environment. The proposed networking stack enables varying levels of encryption across all layers of the communication stack to ensure an easy-to-adopt, secure-by-design network architecture. We also deploy a novel data transformation and fingerprinting-based localization algorithm, which is highly effective in localizing user devices within a given area. The ATLAS framework is open-sourced at https://atlas-tuw.sourceforge.io to enable wide-spread adoption and further research and development.

The influence of friction on machining processes as a function of pressure, velocity and temperature is neither deeply understood nor sufficiently definable for Finite-Element-Method (FEM) simulations. Current simulations therefore often use constant values for the friction coefficients. In this work, friction coefficients for SAE 1045 are determined from different tribometers. An empirical model is subsequently fit to the data and used in different FEM-tools to simulate orthogonal cutting. Results are compared to corresponding experiments. A final evaluation of the model reveals the challenges due to the elasto-plastic contact and thus the derivation and utilisation of such a model.

QDI circuits are robust towards timing issues, but this elasticity makes them vulnerable in value-domain fault scenarios because data-accepting windows are flexibly defined by the handshakes, and during these windows any data transition gets latched, even those originating from single event transients. As a solution, locking the data-accepting windows after the first transition contributes to robustness, but still needs consideration. We examine WCHB variants called Interlocking-WCHB and Input/Output-Interlocking-WCHB in this respect. To highlight the relevant error triggering conditions, we chose two target circuits to investigate the behavior in detail: FIFO and pipelined multiplier. Based on the experimental results we investigate the observed errors to understand the main cause of their generation and propagation. We highlight the problematic scenarios and propose modifications in buffer styles that resolve most of these while minimizing the area overhead to 50%.

The large number of drills and taps in automotive power train components make these processes to a considerable machining step. Due to the fact that hypoeutectic Al-Si alloys tend to adhere on the tool surface, the machinability of these alloys is challenging. In times of modern light-weight design, every gram counts. Therefore material, which is not necessarily needed, is removed from these components, designwise. One result of such steps is an increased number of clearance holes at the power train components. The requirements of short cycle times due to cost reasons induce the manufactures to machine blind holes and clearance holes with one tapping tool to reduce the non-productive time of tool changes. These tools normally have a centred internal coolant supply providing sufficient chip evacuation. Especially the adhesion of Al has a negative influence on the chip transportation and leads to an increase of stochastic inclinations of clogging the chip flute. In course of the present work, it is shown that this tendency increases when the chips are not properly flushed out of the flutes. Obviously this process instability increases when machining clearance holes by tools with a centred internal coolant supply. Sandvik also detected this problem and patented a tapping tool with a central bore and radial coolant channels for every flute in the area of the tool chamfer. According to this idea a tool was designed by finite element method for mechanical structure. Also fluid dynamic studies have been created to determine the lubricant flow. With prototypes of such a tapping tool, cutting tests were performed in Al-Si alloys compared to conventional tapping tools.

Asynchronous circuits, specifically those using a quasi delay-insensitive (QDI) implementation are known for their high resilience against timing uncertainties. However, their event-based operation principle impedes their temporal masking capability, making them more susceptible to fault-induced transitions caused by single event transients. While synchronous circuits obtain high resilience through temporal masking that is established through the sampling of data by flip flops, asynchronous circuits, by design must be flexible about the phases of data validity leaving a larger attack surface for faults. Consequently, previous work has proposed to narrow down the windows in which data changes are accepted, in order to improve the temporal masking in QDI designs.In this paper, we analyze the fault sensitivity of asynchronous QDI circuits when subjected to single event transients. We do so by performing extensive fault injection experiments into different buffer styles to identify parameters that are the main contributors to the fault sensitivity of the circuit and compare their resilience.For that purpose, we use two variants of a multiplier circuit as target circuits. One with the shift and add operations arranged in a linear pipeline, and another one with an internal ring structure that computes the result iteratively, yielding designs with the same logic and buffer implementations, yet very different modes of operation. By varying the buffer styles, we are able to show the difference in robustness as well as the effectiveness of fault mitigation techniques inherent in some buffer styles.