We investigate static scheduling of taskgraphs onto parallel machines where the frequency of processors can be scaled at runtime. Given a deadline until which execution of the resulting schedule must be completed, we aim at minimizing the energy consumed by the parallel processors during execution. We present optimal and heuristic solutions to this problem and partial problems. We quantify the increase in energy consumption when switching from a globally optimal solution via a combination of optimal partial solutions to heuristic solutions. We find that, on our set of benchmark taskgraphs, the increase is 32.56% on average for a combination of heuristic solutions and thus tolerable.

Stream programming abstracts parallelism complexity by modeling a program as a set of streaming tasks. Tasks run repeatedly and can even be internally parallel, i.e., use one or multiple cores simultaneously (moldable). The throughput of the streaming application, as well as its energy consumption, depends strongly on scheduling, i.e., on how tasks are mapped to cores, and on the frequency at which they run. Crown scheduling is a scheduling method that reduces this problem's combinatorial complexity considerably by introducing a few additional restrictions especially on tasks' core allocation sizes and mapping. While it has previously been shown to outperform competing methods, the impact of these restrictions on the schedule quality has, up to now, never been analyzed quantitatively. In this paper, we first propose several crown scheduler improvements toward fewer restrictions. Also, we provide an Integer Linear Programming formulation that solves the same optimization problem without the inherent restrictions of crown scheduling. While in an extreme case an unrestricted schedule might use 3.7 times less energy than a crown schedule for a realistic execution platform model, we show that in practical benchmarks the difference is small while crown schedulers are significantly faster than unrestricted scheduling. We experimentally confirm this with benchmarks derived from random task collections, classic parallel algorithms as well as the Streamit benchmark suite.

Fault tolerance in parallel systems can be achieved by duplicating task executions onto several processing units, so in case one processing unit (PU) fails, the task can continue executing on another unit. Duplicating task execution affects the performance of the system in fault-free and fault cases, and its energy consumption. Currently, there are no tools for properly handling the three-variable optimization problem: Performance \(\leftrightarrow \) Fault Tolerance \(\leftrightarrow \) Energy Consumption, and no facilities for integrating it into an actual system. We present a fault-tolerant runtime system (called RUPS) for user defined schedules, in which the user can give their preferences about the trade-off between performance, energy and fault tolerance. We present an approach for determining the best trade-off for modern multicore architectures and we test RUPS on a real system to verify the accuracy of our approach itself.

We investigate how to explore with a parallel machine a random and unknown forest, of which we only know an upper bound on the total size, some leaves to start from, and the roots. The size of the forest is too large to represent it explicitly in the machine's main memory. Instead for each node, its parent node is given by an oracle, i.e. a piece of code of which no particulars may be known. We present a parallel algorithm, and use experiments to find parameter settings that influence the runtime favorably

We present the concept of mapped taskgraphs, which comprise all information of a static taskgraph and the corresponding static schedule. Mapped taskgraphs allow to reason about and optimize static schedules for taskgraphs in the language of graphs. This allows to employ the wealth of graph algorithmics, and still be able to extract easily a schedule with a task order similar to the original schedule, but possibly smaller makespan. We prove that our construction has the above properties, and present two exemplary applications that use mapped taskgraphs. One is new, the other a number of years old but only mentions a variant of this technique in passing and thus does not explicitly or formally explain it or deal with it.

Cryptographic applications like symmetric encryption algorithms can be implemented either in bit-slice or word-parallel fashion. The conversion between the two data representations corresponds to transposing a bit-matrix with variables as row vectors. In previous work we have demonstrated that combining the best of both variants, i.e. executing part of the code in bit-slice, and part of the code in word-parallel manner, can improve performance considerably, but most of the advantage is spent for the conversion. Here, we examine the conversion routine closer and deviate different levels of hardware and software support that can accelerate the conversion, ranging from existing but seldom used instructions to completely new instructions that might be implemented in future systems. We quantify the acceleration achieved by each level of support, and provide preliminary experimental results.

Workflows of dependent tasks are a widespread model for parallel applications, often statically scheduled prior to application. Static schedules can tolerate processor failures due to permanent faults by placing duplicate tasks during the scheduling process. Schedules for workflows with deadlines can be extended to include frequency scaling information to optimize energy consumption. Frequency scaling can also be used in case of a fault to minimize its effects on the schedule makespan, however for the price of additional energy consumption. We investigate the interplay between these two parameters and quantify the energy increase to be expected in case of a fault and a given makespan increase. This knowledge enables the user to inform the scheduler about the makespan increase that is tolerable in case of a fault, where tolerable includes both the related performance aspects and the expected increase in energy. To achieve this, we model small taskgraphs from a benchmark suite as integer linear programs and determine with the help of a solver energy-optimal schedules for the fault-free case and for all possible fault positions with several levels of makespan increase. We present averages and distribution depending on makespan increase for a processor with hypothetical power profile. Additionally, we present two heuristics to modify task frequency settings in case of a fault, to restrict the makespan increase to a given value. Comparison with optimal frequency settings from the benchmark suite indicate that the heuristics only incur a small energy overhead.

Many-core systems provide a great performance potential with the massively parallel hardware structure. Yet, these systems are facing increasing challenges such as high operating temperatures, high electrical bills, unpleasant noise levels due to active cooling and high battery drainage in mobile devices; factors caused directly by poor energy efficiency. Furthermore by pushing the power beyond the limits of the power envelope, parts of the chip cannot be used simultaneously – a phenomenon referred to as “dark silicon”. Power management is therefore needed to distribute the resources to the applications on demand. Traditional power management systems have usually been agnostic to the underlying hardware, and voltage and frequency control is mostly driven by the workload. Static schedules, on the other hand, can be a preferable alternative for applications with timing requirements and predictable behavior since the processing resources can be more precisely allocated for the given workload. In order to efficiently implement power management in such systems, an accurate model is important in order to make the appropriate power management decisions at the right time. For making correct decisions, practical issues such as latency for controlling the power saving techniques should be considered when deriving the system model, especially for fine timing granularity. In this paper we present an accurate energy model for many-core systems which includes switching latency of modern power saving techniques. The model is used when calculating an optimal static schedule for many-core task execution on systems with dynamic frequency levels and sleep state mechanisms. We derive the model parameters for an embedded processor with the help of benchmarks, and we validate the model on real hardware with synthetic applications that model streaming applications. We demonstrate that the model accurately forecasts the behavior on an ARM multicore platform, and we also demonstrate that the model is not significantly influenced by variances in common type workloads.

Static schedules can be a preferable alternative for applications with timing requirements and predictable behavior since the processing resources can be more precisely allocated for the given workload. Unused resources are handled by power management systems to either scale down or shut off parts of the chip to save energy. In order to efficiently implement power management, especially in many-core systems, an accurate model is important in order to make the appropriate power management decisions at the right time. For making correct decisions, practical issues such as latency for controlling the power saving techniques should be considered when deriving the system model, especially for fine timing granularity. In this paper we present an accurate energy model for many-core systems which includes switching latency of modern power saving techniques. The model is used when calculating an optimal static schedule for many-core task execution on systems with dynamic frequency levels and sleep state mechanisms. We create the model parameters for an embedded processor, and we validate it in practice with synthetic benchmarks on real hardware.

We investigate deadline scheduling of independent tasks on parallel processors with discrete frequency levels, when the latency for frequency scaling cannot be neglected. This situation frequently occurs in applications, e.g. streaming applications with soft real-time requirements. We demonstrate that previous algorithms for energy-optimal static scheduling of independent tasks are non-optimal in this setting. We present a scheduling heuristic based on bin packing with a cost function that takes latency for frequency scaling into account. We evaluate our heuristic against previous approaches with benchmark task sets and achieve energy reductions between 3% and 13%. We further demonstrate that for a concrete embedded multicore processor, the power curves vary over the identical cores, so that the processor looks heterogeneous from a power perspective. We adapt our bin packing heuristic and demonstrate that for the benchmark task sets, further energy reductions up to 4% can be achieved.

Exploiting effectively massively parallel architectures is a major challenge that stream programming can help facilitate. We investigate the problem of generating energy-optimal code for a collection of streaming tasks that include parallelizable or moldable tasks on a generic manycore processor with dynamic discrete frequency scaling. Streaming task collections differ from classical task sets in that all tasks are running concurrently, so that cores typically run several tasks that are scheduled round-robin at user level in a data-driven way. A stream of data flows through the tasks and intermediate results may be forwarded to other tasks, as in a pipelined task graph. In this article, we consider crown scheduling, a novel technique for the combined optimization of resource allocation, mapping, and discrete voltage/frequency scaling for moldable streaming task collections in order to optimize energy efficiency given a throughput constraint. We first present optimal offline algorithms for separate and integrated crown scheduling based on integer linear programming (ILP). We make no restricting assumption about speedup behavior. We introduce the fast heuristic Longest Task, Lowest Group (LTLG) as a generalization of the Longest Processing Time (LPT) algorithm to achieve a load-balanced mapping of parallel tasks, and the Height heuristic for crown frequency scaling. We use them in feedback loop heuristics based on binary search and simulated annealing to optimize crown allocation. Our experimental evaluation of the ILP models for a generic manycore architecture shows that at least for small and medium-sized streaming task collections even the integrated variant of crown scheduling can be solved to optimality by a state-of-the-art ILP solver within a few seconds. Our heuristics produce makespan and energy consumption close to optimality within the limits of the phase-separated crown scheduling technique and the crown structure. Their optimization time is longer than the one of other algorithms we test, but our heuristics consistently produce better solutions.

Taskgraphs model a broad range of parallel applications. Despite static scheduling, processor failures can be overcome with the help of task duplication, which we explored in a previous proposal. With the advent of processor frequency scaling, energy can be saved by the runtime system as it is informed about gaps in the schedule and task dependencies, and thus can slow down processors as long as dependencies do not lead to a makespan increase. In the case of a fault, a makespan increase can be traded for additional energy investment by accelerating the task duplicates that run tasks from the crashed core. We evaluate our proposal with a large benchmark suite of taskgraphs with different sizes for a generic manycore architecture.

High performance servers of heterogeneous computing environments, as can be found in data centers for cloud computing, consume immense amounts of energy even though they are usually underutilized. In times when not all computing capabilities are needed the task to be solved is how to distribute the computational load in a power-efficient manner. The question to be answered is, what load partitions should be assigned to each physical server so that all work is done with minimal energy consumption. This problem is closely related to the selection of physical servers that can be switched off completely to further reduce the power consumption. In this work, we present algorithms which calculate a power-efficient distribution of a divisible workload among multiple, heterogeneous physical servers. We assume a fully divisible load to calculate an optimized utilization of each server. Based on this distribution, an iterative process is carried out to identify servers, which can be switched off in order to further reduce the power consumption. With that information, workload (re)distribution can take place to partition appropriate subloads to the remaining servers. As before, the calculated partitioning minimizes the power consumption.

High performance servers of data centers for cloud computing consume immense amounts of energy even though they are usually underutilized because they provide huge computing capabilities. In times when not all of those computing capabilities are needed the task to be solved is how to distribute the load in a power-efficient manner. The research question is: How should a requested compute load be mapped to the available physical servers so that it is executed with the minimum power consumption? The requested load is measured in operations per seconds and changes over time. In this work, we assume that it is divisible which means that portions of the requested load can be freely assigned to different servers. This assumption is plausible because the load of a typical compute cloud consists of many virtual machines (VM). Our investigations are based on the SPECpower benchmark, retrieved Jan 9, 2013. SPECpower relies on Server Side Java (SSJ) for measuring power consumption of servers at different load levels running Java applications [7].

We investigate the problem of generating energy-optimal code for a collection of streaming tasks that include parallelizable or malleable tasks on a generic many-core processor with dynamic discrete frequency scaling. Streaming task collections differ from classical task sets in that all tasks are running concurrently, so that cores typically run several tasks that are scheduled round-robin at user level in a data driven way. A stream of data flows through the tasks and intermediate results are forwarded to other tasks like in a pipelined task graph. In this paper we present crown scheduling, a novel technique for the combined optimization of resource allocation, mapping and discrete voltage/frequency scaling for malleable streaming task sets in order to optimize energy efficiency given a throughput constraint. We present optimal off-line algorithms for separate and integrated crown scheduling based on integer linear programming (ILP). We also propose extensions for dynamic rescaling to automatically adapt a given crown schedule in situations where not all tasks are data ready. Our energy model considers both static idle power and dynamic power consumption of the processor cores. Our experimental evaluation of the ILP models for a generic manycore architecture shows that at least for small and medium sized task sets even the integrated variant of crown scheduling can be solved to optimality by a state-of-the-art ILP solver within a few seconds.

We present an approach to find application-specific optimal positions for memory controllers within the on-chip network of a manycore processor. The approach uses benchmark applications to represent target load, and considers computational load balance, task-to-task communication, and task-to-memory communication to model performance for a particular memory controller configuration, where the relative priorities of those criteria can be chosen by the user. A simulated annealing approach is used to find the best memory controller configuration. We use the on-chip network of the Intel SCC as a test case and find that for several applications, the positions of the memory controllers are different from their real positions. The approach can be extended to also determine the appropriate number of memory controllers, i.e. the minimum number to achieve a certain performance level.