'Pseudo' Laue diffraction experiments, with multi pink beam, is being considered as an option for the upgrade of SOLEIL for fast time resolved crystallographic applications in the energy range from 5 to 30 keV. An important requirement for the detector of such experiments is to increase the readout speed and the capability to discriminate between several energies. For this purpose, a new project has been launched in 2021 through a collaboration between SOLEIL and AGH, starting with a feasibility phase with the design and realization of a new photon counting ASIC prototype, named UFERI (Ultra -Fast Energy Resolved Imager). After a short description of the ASIC requirements and main architecture, first results of the ASIC prototypes are presented, as well as preliminary results of the first hybrid pixel modules illuminated with X-rays in our laboratory.

This paper presents the design and measurement results of a prototype integrated circuit (IC) of pixel architecture operating in single photon counting mode with real-time interpixel communication. The prototype IC is designed in the CMOS 40 nm process and its core is a matrix of 32 × 64 pixels of 50 μm pitch. Each pixel contains fast front-end analog electronics, a set of discriminators, ripple counters and digital blocks implementing relocation algorithms. These algorithms utilize interpixel communication to benefit from charge sharing effect by increasing the detector spatial resolution beyond the limit determined by pixel pitch. Using the bump-bonding technique, the IC was connected to a pixelated semiconductor detector with 400 μm thickness and tested using a 16 keV synchrotron monochromatic X-ray beam at the European Synchrotron Radiation Facility.

Using time -domain integration (TDI) and a two-dimensional sensor is beneficial for X-ray imaging of moving objects. Applying on -chip instead off -chip TDI decreases the required data throughput between an ASIC and the backend several times [1]. This, in turn, allows us to significantly simplify the ASIC itself as well as the backend. We present the results of test measurements of an ASIC dedicated for X-ray material discrimination by using on -chip TDI and a CdTe sensor. The main part of the ASIC is an 192 x 64 pixel matrix. The pixel size is 100 mu m x 100 mu m, so the chip size is approximately 6.7 mm x 2 cm. The chip is manufactured in a 130 nm CMOS technology with 8 metal layers. A single pixel analog front-end consists of a charge -sensitive amplifier, a shaper, and three discriminators followed by counters. The test was conducted with a 0.75 mm thick CdTe sensor. First, we show the results of the discriminator offset correction followed by the evaluation of the pixel analog front-end gain and noise conducted with single energy radiation. Next, the results of moving objects imaging are obtained by using an industrial X-ray machine for food inspection (continuous energy spectrum). This is carried out to present an example of the image and evaluate the image signal to noise ratio for different energy discriminator thresholds, sensor bias voltages, detector module temperatures and object speeds.

As a follow-up of a Signal-to-Noise Ratio (SNR) study presented previously, this work discusses the experimental results obtained for the statistical analysis of photon counting detector measurements. The test device is a hybrid assembly built with a pixelated 400 mu m thick electron collection Si sensor bump-bonded to a SPHIRD test readout ASIC. The analog front-end in each pixel of the ASIC produces a pulse of tens of nanoseconds for each X-ray hit, and its digital circuitry implements both amplitude and time-based pile-up compensation methods, making this device an excellent candidate for this study. Under pile-up conditions, the SNR of the photon counting measurements deviates from Poisson statistics and it has been evaluated by applying the numerical method introduced in a previous work. In addition to standard photon counting operation, two pile-up compensation methods implemented in SPHIRD were tested. The results were evaluated for individual pixels. The standard photon counting results reproduce the simulated behavior, presenting a SNR response that peaks around 30% pile-up, and then drops. Meanwhile, both pile-up compensation methods have presented a comparable effect on improving not only the count rate also the statistical response of the system, for the covered count-rate range of up to 45Mcps/pixel. The obtained results validate the presented methodology to obtain the SNR, also elucidating pile-up detrimental effect on the statistical quality of the data.

Hybrid Pixel Detectors (HPDs) have become popular in particle and photon detection techniques in recent years. This type of devices consists of two parts: a pixelated sensor (based on Si, Ge, GaAs, CZT, etc.), and a readout Integrated Circuit (IC), which usually contains thousands of pixels and millions of transistors. ICs suffer from the inaccuracies of manufacturing processes, therefore HPDs have to be thoroughly tested before the sensor bump -bonding process. This paper presents a highly efficient system for the automated testing of pixelated HPDs. The presented solution is based on the Intel Arria 10 GX Field Programmable Gate Array (FPGA) development kit and a Linux-powered Personal Computer (PC), connected via Peripheral Component Interconnect Express (PCIe) 8x Gen. 3 interface. The proposed system has been built of well -thoughtout modules connected through the set of precisely defined interconnects. This approach enabled the development of an architecture that may be easily implemented in both PCIe-based systems and System -on -Chip devices, such as Intel Agilex SoC. The presented system has been tested with both a manufactured IC and a model implemented in the FPGA.

This brief presents the design and measurement results of a prototype SPHIRD-1 ASIC in the CMOS 40 nm process. The chip is dedicated to high count rate single photon counting operation at the European Synchrotron Radiation Facility with Extremely Brilliant Source. The core of the prototype IC is the matrix of $64\times32$ pixels of $50 \mu \text{m}$ pitch. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and a detector leakage current compensation circuit. The CSA is connected to a set of three discriminators. The readout channel is equipped with additional circuits, which provide different pulse pile-up compensation methods. The priority of the analog front-end electronics is to process the input signal in a short time (the CSA output pulse time width is only 18 ns) and to keep low noise (the equivalent noise charge at the level of 188 el. rms) with a power consumption equals to $26 \mu \text{W}$ /pixel. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. The measurements prove the possibility of counting up to 11.5 Gcps/mm 2 based on a 10% dead time loss input rate parameter.

Semiconductor strip sensors applied as solid-state radiation or particle detectors can be used in radiation detection and measurement for various applications in particle physics experiments, X-ray imaging (e.g. medical), or material science. The X-ray imaging devices with spectroscopic and position resolution features are a very important research topic at many institutes and companies worldwide. Short strip silicon detectors are good candidates for X-ray spectroscopy, because of their relatively small capacitance and leakage current. If additionally, strip pitch is below 100 μm, then the high spatial resolution is also possible. In this paper, the analysis and noise optimization of the read-out electronics for short silicon strip detectors with Charge Sensitive Amplifier (CSA) and shaping amplifier (shaper) is presented. The CSA is optimized for the detector capacitance of around 1.5 pF, and the shaper nominal peaking time is about 1 μs (controlled by the sets of switches). We take into account the sources of noise in a radiation imaging system (current parallel noise, voltage series noise, and 1/f or flicker series noise) both internal (related to the front-end electronics itself) but also external, stemming from a sensor, interconnect, or printed circuit board parasitic components. We target the noise level below 40 el. rms, considering low power consumption (a few mW) and limited channel area.

Hybrid pixel detectors are segmented devices used for X-ray detection that consist of a sensor attached to the readout electronics. Detectors working in single-photon counting mode process each incoming photon individually, have essentially infinite dynamic range, and by applying energy discrimination they provide noiseless imaging. To improve the resolution of the detector and allow operation with high-intensity photon fluxes, the pixel size is reduced. However, with decreasing pixel size, a charge sharing effect is more prominent. This leads to false event registration or omitting the event, and degradation of the energy resolution of the detector. Algorithms aiming at reducing the influence of charge sharing have already been implemented on-chip. However, the spatial resolution of the detector can be increased beyond the physical size of the pixel if the charge proportions collected by neighboring pixels are analyzed. The simulations show that charge cloud size referred to pixel size and noise are the key parameters that determine the accuracy of the subpixel algorithm. The article shows the concept of subpixel algorithm and the simulations for different detector parameters and approximation algorithms. The slanted-edge method was implemented to quantify the resolution of detectors consisting standard readout architecture. The chips were simulated and tested to verify the influence of different bias voltages, sensor materials, and thicknesses on charge sharing and as a consequence on the detector resolution. The simulated and measured edge spread functions were compared. The results show that the simulator can be used to describe the spatial resolution of the detectors, and can be used for further studies of the resolution of detectors with subpixel algorithm implemented.

The paper presents the design and measurements of a low noise integrated circuit in a CMOS 130 nm for the readout of a hybrid pixel detector operating in a single photon counting mode. A core of IC contains a matrix of $128\times256$ square shaped pixels of $75~\mu \text{m}$ pitch. Each readout pixel consists of a charge sensitive amplifier (CSA), a shaper, two discriminators, and two 14-bit counters. We present the novel CSA feedback circuitry with an effective resistance of 0.6 $\text{G}\Omega $ and sets of switches, which allows low noise operation and fast return to the CSA output baseline at the same time providing the possibility of operation with a higher flux of input pulses. The measured equivalent noise charge of IC (bump-bonded to silicon sensor) is only 44 $\text{e}^{-}$ rms at 15°C, the offset spread is 5.5 $\text{e}^{-}$ rms and the energy resolution is FWHM = 380 eV @ 8keV, which is currently the best result in single photon counting pixel detectors. The hybrid pixel detector can register up to 107 million photons/mm2 per second, while the power consumption per single pixel is about $42~\mu \text{W}$ .

This paper presents the design and simulation of a prototype chip in the CMOS 40 nm process for high spatial resolution operation at the ESRF-EBS synchrotron. The core of the prototype IC is the pixel matrix with 50 mu m pitch, operating in a single photon counting mode. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and detector leakage current compensation circuit. The CSA output is directly connected to the discriminator with an offset trimming capability. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. Furthermore, several algorithms of interpixel communication are implemented in the chip to increase detector spatial resolution by using the charge sharing effect.

This work presents a summary of the experimental results and the performance obtained from a first set of p-type silicon SPHIRD prototypes. The SPHIRD project (Small Pixel High Rate photon counting Detector) targets a new generation of X-ray photon counting hybrid pixel detectors for synchrotron radiation applications, with small pixels and operating between 10 and 30 keV. The readout ASIC is designed to explore techniques that boost the count rate capabilities of the detector and methods to manage, or in some cases exploit, the effects of charge sharing that are unavoidable with small pixels in this type of detector. The achievement of high photon rates relies on the implementation of a fast charge-sensitive amplifier in the pixel in combination with pile-up compensation techniques, which have been compared experimentally. The obtained results show and quantify their effectiveness in increasing the count-rate handled by the detector. The readout chip also includes dedicated circuitry for the relocation of photon hits, a functionality necessary to reduce the photon losses that are observed in photon counting detectors due to charge sharing when the discrimination threshold is set to 50% of the photon energy. The circuitry is however not limited to full pixel relocation: it also implements resources to reassign X-ray hits within regions smaller than the physical pixel. All these operation modes were experimentally evaluated with a pencil beam and with full field images.

The dynamic development of multiple types of sensors of physical quantities requires the development of new electronic systems adapted to them.High-density multichannel ionizing radiation sensors are used in industrial and medical imaging as well as in high-energy physics experiments.Likewise, multichannel sensor systems are used to record biomedical signals.In both cases, when reading sensors, specialized ASIC integrated circuits are used, which allow the construction of detection systems with good measurement parameters while maintaining low power consumption.The following article presents selected examples of integrated readout circuits designed in the microelectronic group of the Department of Measurement and Electronics at AGH UST in Krakow.

The SPHIRD project is a study towards the development of a new generation of X-ray photon counting pixel detectors for synchrotron radiation applications operating between 10 and 35 keV, with very high count rate capabilities and small pixels. The study relies on the design and construction of test prototypes complemented by detector simulations. The strategy to boost count rate consists in combining a fast analog front-end with pile-up compensation techniques and the option of pixel binning. The project intends to explore and compare different time-based and amplitude-based pile-up compensation methods. As a complementary study, the project is investigating the exploitation of charge sharing in very small pixels to relocate photon hits within sub-pixel matrices and increase the effective spatial resolution of the detectors. The first SPHIRD prototypes consist of small 64×32 pixel matrices with p-type Si pixelated sensors bonded to a test readout integrated circuit designed in CMOS 40nm technology. Although the test prototypes are built with 50 µm pixels, one of the objectives of the study is to explore how small the pixels could be potentially made in a final system.

This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).

X-ray imaging of moving objects using line detectors remains the most popular method of object content and structure examination with a typical resolution limited to 0.4–1 mm. Higher resolutions are difficult to obtain as, for the detector in the form of a single pixel row, the narrower the detector is, the lower the image Signal to Noise Ratio (SNR). This is because, for smaller pixel sizes, fewer photons hit the pixel in each time unit for a given radiation intensity. To overcome the trade-off between the SNR and spatial resolution, a two-dimensional sensor, namely a pixel matrix can be used. Imaging of moving objects with a pixel matrix requires time-domain integration (TDI). Straightforward TDI implementation is based on the proper accumulation of images acquired during consecutive phases of an object’s movement. Unfortunately, this method is much more demanding regarding data transfer and processing. Data from the whole pixel matrix instead of a single pixel row must be transferred out of the chip and then processed. The alternative approach is on-chip TDI implementation. It takes advantage of photons acquired by multiple rows (a higher SNR), but generates similar data amount as a single pixel row and does not require data processing out of the chip. In this paper, on-chip TDI is described and verified by using a single photon counting two-dimensional (a matrix of 128 × 192 pixels) CdTe hybrid X-ray detector with the 100 µm × 100 µm pixel size with up to four energy thresholds per pixel. Spatial resolution verification is combined with the Material Discrimination X-ray (MDX) imaging method.

A new fast single photon counting hybrid pixel detector has been developed at SOLEIL Synchrotron to carry out multi-probe time resolved diffraction experiments at high repetition rate. Although the detector has been initially designed for the interest of these experiments, thanks to its promising detection performance and various fast acquisition mode, its use is being continuously extended to applications at other beamlines at SOLEIL, for existing and/or new applications, e.g., coherent imaging, energy dispersive X-ray absorption spectroscopy, X-ray reflectivity, X-ray photon correlated spectroscopy that requires high detection sensibility and high dynamic range at moderate energy below 6 keV. To fulfill the various demands, two detector prototype versions have been designed and realized: one with a square shaped active area of 2 × 2 cm 2 and another one with a rectangular active area of 1 × 4 cm 2 . In this work, performance of the detector and preliminary results obtained on beamlines are presented. The next step consists to develop a larger detector and its status is briefly presented as well.

Spectrally selective X-ray imaging provides improved material and tissue discrimination in comparison with the state-of-the-art dual energy technologies that are commonly used in medical, industrial, and security applications. Cadmium telluride (CdTe)- and cadmium zinc telluride (CdZnTe)-based line scanners and small size two-dimensional X-ray sensors are emerging to the market, but the need for large-scale panels is axiomatic. In this study, a seamless CdTe tile was developed that enables the implementation of large-sized, energy selective X-ray detector panels. The developed tile consists of a $64\times64$ pixel array (with $150~\mu \text{m}$ pitch) with a necessary substrate, ASIC, and CdTe crystal. The performance of the constructed seamless tile was characterized by focusing on spectral resolution and stability. In addition, a simple pixel trimming method that automates the equalization of each energy selective pixel was developed and analyzed. The obtained results suggest that the proposed concept of seamless (tileable) detector structures is a feasible approach to scale up panel sizes. The seamless tile shows comparable spectral resolution and stability performance with commercial CdTe sensors. The effect of tile to tile variation, the realization of a large-scale panel, as well as the charge sharing performance were left out of the scope and are to be studied in the next phase.

Hybrid photon counting (HPC) detectors are widely used at both synchrotron facilities and in-house laboratories. The features of HPC detectors, such as no readout noise, high dynamic range, high frame rate, excellent point spread function, no blurring etc. along with fast data acquisition, provide a high-performance detector with a low detection limit and high sensitivity. Several HPC detector systems have been developed around the world. A number of them are commercially available and used in academia and industry. One of the important features of an HPC detector is a fast readout speed. Most HPC detectors can easily achieve over 1000 frames s−1, one or two orders of magnitude faster than conventional CCD detectors. Nevertheless, advanced scientific challenges require ever faster detectors in order to study dynamical phenomena in matter. The XSPA-500k detector can achieve 56 kframes s−1 continuously, without dead-time between frames. Using `burst mode', a special mode of the UFXC32k ASIC, the frame rate reaches 1 000 000 frames s−1. XSPA-500k was fully evaluated at the Metrology beamline at Synchrotron SOLEIL (France) and its readout speed was confirmed by tracking the synchrotron bunch time structure. The uniformity of response, modulation transfer function, linearity, energy resolution and other performance metrics were also verified either with fluorescence X-rays illuminating the full area of the detector or with the direct beam.

Nanoparticles are under investigation as diagnostic and therapeutic agents for joint diseases, such as osteoarthritis. However, there is incomplete understanding of nanoparticle diffusion in synovial fluid, the fluid inside the joint, which consists of a mixture of the polyelectrolyte hyaluronic acid, proteins, and other components. Here, we show that rotational and translational diffusion of polymer-coated nanoparticles in quiescent synovial fluid and in hyaluronic acid solutions is well described by the Stokes-Einstein relationship, albeit with an effective medium viscosity that is much smaller than the macroscopic low shear viscosity of the fluid. This effective medium viscosity is well described by an equation for the viscosity of dilute polymer chains, where the additional viscous dissipation arises because of the presence of the polymer segments. These results shed light on the diffusive behavior of polymer-coated inorganic nanoparticles in complex and crowded biological environments, such as in the joint.

This paper presents a readout integrated circuit of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in high-energy X-ray imaging applications. The MPIX IC of the area of $9.6\ \text{mm} \times 20.3\ \text{mm}$ is designed in a CMOS 130 nm process. The IC core is a matrix of $96\times 192$ square-shaped pixels of $100\ \mu \mathrm{m}$ pitch. Each pixel contains an analog front-end, four independently working discriminators, and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray color imaging). The MPIX chips are bump-bonded to pixel CdTe sensor with a pitch of $100\ \mu \mathrm{m}$ and thickness of $750\ \mu \mathrm{m}$. These hybrid detectors (sensor bump-bonded to readout integrated circuit) are characterized by test pulses and X-ray radiation. To match the different range of applications the MPIX chip has 8 possible different gain settings. In the high gain mode, the chip can operate with Xray photons up to 46 keV and has the Equivalent Noise Charge (ENC) of 123 el. rms. In the low gain mode, the ENC is equal to 192 el. rms, and the chip can process the X-ray photons of energy up to 154 keV. The matrix of 18432 pixels has a very good uniformity: globally set threshold has an effective pixel to pixel offset spread of 1 mV (for the full threshold range up to 800 mV). The power consumption per pixel is $80\ \mu \mathrm{W}/\text{pixel}$. Additionally, to deal with charge sharing effects in a thick semiconductor pixel sensor, Multithreshold Pattern Recognition algorithms are implemented in the MPIX IC.