Parallel architectures with shared memory are well suited to many applications, provided that efficient shared memory access and process synchronization mechanisms are available. When the parallel machine is a cluster with physically distributed memory, software based synchronization mechanisms together with virtual memory infrastructure can implement Software Distributed Shared Memory (S-DSM), a shared memory abstraction on a distributed memory machine. However, the communication network overload from the emulation can limit the performance of such systems. This problem motivated our research, in which we developed a set of synchronization primitives for S-DSM on reconfigurable hardware. This hardware implements an auxiliary synchronization network, which works in parallel to the data communication network. Experiments evaluating our hardware implementation against a software one showed that our system increases the performance of these S-DSM primitives by a factor of 40 or more.

Simulation results are presented using the hardware-implemented, trace-based dynamic instruction scheduler of our single process DTSVLIW architecture to schedule instructions from several processes into multiple streams of VLIW instructions for execution by a wide-issue, simultaneous multi-threading (SMT) execution engine. The scheduling process involves single instruction execution of each process, dynamically scheduling executed instructions into blocks of VLIW instructions cached for subsequent SMT execution: SMT provides a mechanism to reduce the impact of horizontal and vertical waste, and variable memory latencies, seen in the DTSVLIW. Preliminary experiments explore this extended model. Results achieve PE utilization of up to 87% on a 4-thread, 1-scalar, 8 PE design, with speed-ups of up to 6.3 that of a single processor. Noticeably it only needs a single scalar process to be scheduled at any time, with main memory fetches being 1–4% that of a single processor.

Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism (ILP) with backward code compatibility. This paper presents the effect of multicycle instructions on the performance of a DTSVLIW architecture running the SPECint95 benchmarks.

A multi-threaded, dynamically trace-based architecture is presented, designed to make fuller usage of the PEs of a VLIW. The mDTSVLIW extends our single process DTSVLIW design to reduce the effect of both horizontal and vertical waste, and of variable latencies. The DTSVLIW performs single instruction execution of a process, dynamically scheduling these in hardware into blocks of VLIW instructions for VLIW execution. The mDTSVLIW maintains these features and adds simultaneous multithreading by issuing and executing instructions from VLIW blocks from several threads. Preliminary experiments to explore the design varied the number of threads, scalar processors and cache sizes. Results achieve PE utilization of up to 87% on a 4-thread, 1- scalar, 8 PE design, with speed-ups of up to 6.3 that of a single processor. Noticeably it only needs a single scalar process to be scheduled at any time, with main memory fetches being 1-4% that of a single processor.

This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.

This paper presents an architecture that has been developed to implement neural networks for control and signal processing applications. This architecture offers a single chip solution that can be used standalone in small and medium sized systems, or operate as a preprocessor in larger applications. The constraints imposed on this architecture are discussed, and the methods used to satisfy these are presented. The design of a fully integrated neural processor using this architecture is proposed, and the application development tools are discussed.

Very long instruction word (VLIW) machines potentially provide the most direct way to exploit instruction-level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. In addition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or functional units with different latencies. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Preliminary measurements of the DTSVLIW performance, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented.

Due to the temporal execution locality present in programs, even small instruction caches (16-Kbyte) can provide processors with fast access to instructions most of the time. The Dynamically Trace Scheduled VLIW (DTSVLIW) architecture exploits programs’ temporal execution locality by executing code in two distinct modes. In the first execution encounter, fragments of the code are executed in sequential mode (in a simple pipelined processor), scheduled into blocks of VLIW instructions and cached in a VLIW cache by the DTSVLIW’s Scheduler Engine. In subsequent encounters, the DTSVLIW’s VLIW Engine executes these blocks in VLIW mode. In this paper, we present experiments which show that DTSVLIW machines can perform better than Superscalar machines with equivalent hardware and better than VLIWs with the same degree of parallelism, while keeping the fast clock of the latter. We also discuss how the DTSVLIW compares with the Trace Cache and EPIC architectures.

Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism with backward code compatibility. This paper presents preliminary SPECint95 performance mesuraments of the DTSVLIW architecture, obtained with a simulator which has been implemented in C.