Open-source instruction set architectures have greatly helped excel software development. One of the potential architectures is the RISC-V architecture which gained significant attention due to its providing flexibility, extensibility, and scalability for a wide range of computing systems. Optimizing compilers has become a vital tool for enhancing software performance since software is essential to utilizing RISC-V architectures to their fullest potential. The impact of compiler optimization in the RISC-V ecosystem is examined in this review. We go over the significance of compilers, how to optimize them, and a thorough comparison between the GNU compiler collection (GCC) and low-level virtual machine (LLVM) compilers. This study also explores the possibilities and difficulties of incorporating custom instructions into LLVM to take advantage of the special characteristics of RISC-V architectures. It also demonstrates the importance of compiler optimization in enhancing software performance, decreasing code size, and facilitating effective resource utilization in the RISC-V ecosystem through a thorough analysis. In addition, future research directions are identified, such as heterogeneous computing, energy efficiency, performance modeling, compiler-enabled security measures, advanced optimization techniques, support for specialized RISC-V extensions, and domain-specific languages. Investigating these avenues will facilitate the wider adoption and development of this open-source processor architecture by opening the door for more effective and performant software on RISC-V architectures.
Quite often, cache performance is a deterministic factor of throughput, latency, and power efficiency in current multi-core processor architecture specially when it is subject to data-intensive routines in scientific computing, artificial intelligence, and large-scale cloud workloads. Existing machine learning techniques are effective in some cases but often inaccurate or difficult to scale to large workload sets because they require training on the computing platform whereas traditional cache simulators, though accurate, are far too slow to simulate multi-terabyte execution traces. This study proposes CachePredictML, a machine learning system that uses big data to predict the similarities of the cache behavior on multi-core processors. The framework can use a distributed preprocessing pipeline using Apache Spark and HDFS to process up to 4.6 TB of memory access traces of SPEC CPU2017, PARSEC 3.0 and SPLASH-2 benchmarks being run on 16-core Intel Xeon Platinum 8380 and 64-core AMD EPYC 7742 processors. Our Hybrid-Grid solution extracts temporal locality, spatial locality, and reuse distance, and with workload characterization using Random Forest, Gradient Boosting and LSTM networks, plus Graph Neural Networks to model coherence patterns, workload characterization is provided. VO results indicate that CachePredictML delivered 92.34 percent accuracy in prediction, 4.5 percent error in predicting miss ratio, and a 13.4-h reduction in simulation time in contrast to existing state of art ML-based cache predictors. These results demonstrate the power of CachePredictML to speed-up the design-space exploration process, help to tune the cache management policies, and further enable scaleable prediction in a multi-core environment.
Implicit parallel programming models typically give less parallelism control to the programmer, but require less specialised expertise. Explicit parallel models, on the other hand, give much greater parallelism control, but can require significant expertise from the programmer. In this paper, we introduce a novel semi-implicit parallel model, called Elysium, for Idris. Elysium therefore demonstrates semi-explicit parallelism for an emerging class of languages known as dependently-typed languages. These dependently-typed languages encourage safer software via their ability to express strong logical guarantees, in the form of proofs, directly in code. Our semi-implicit approach is based on a process model that uses dependent types to guarantee parallelism properties. We demonstrate how we can use this semi-implicit process model to build common algorithmic skeletons, including farms, pipelines and divide and conquer skeletons. We evaluate our process skeleton approach on a number of examples, achieving speedups of up to 22 on a 28-core machine.
We ported a tomographic reconstruction code from MPI to OpenMP (formally, the software systems Message Passing Interface and Open Multi-Processing). Due to randomness associated with the order of floating point operations, we found that verifying the correctness of the port required a statistical comparison of the answers. These agree within acceptable bounds. As a function of iteration number, the solutions generated with different numbers of cores at first diverge, then converge. We also studied the effect of having different random number starts. In this case, the answers always converge toward each other, although their variation is greater than the variation associated with changing the number of cores with a fixed random number seed.
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simularor (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce parti-gem5, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, parti-gem5 supports gem5’s timing mode, the O3CPU, and Ruby’s custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7 × when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, we show that these can be minimised by setting a quantum based on the latencies of the target system. A quantum value just below the hit latency of the shared cache leads to an error in simulated time below 5
Compliance testing is mandatory when implementing the hardware architecture of a specific instruction set. The official compliance test suite with handwritten test cases for RISC-V can be helpful for this task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations, or include an additional co-processor. This paper uses the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method verifies the functionality within the same test program without requiring a golden reference model (e.g., simulator) and speeds up post-silicon validation times. With extensions to cover all possible hardware architecture implementation hazards and cache misses, a 6 pipeline-stages RV32IM hardware architecture implementation is verified functionally, reaching up to 100
An increasing number of sensors and actuators are being used in today’s high-tech drilling tools to further optimize the drilling process. Each sensor and actuator either generates data that needs to be processed or requires real-time input control signals. RISC-V processors are being developed to meet the computational demands of today’s applications. A known bottleneck for processors is the data flow and instruction input to the processor, especially as memory response times are particularly high for the state-of-the-art harsh environment silicon-on-insulator (SOI) technology. This paper presents a high-performance instruction fetch architecture that achieves a high clock frequency while preserving high instructions per cycle. We evaluate different approaches implementing and propose a design that is able to reach up to 0.8 instruction per cycle (IPC) with a clock frequency of 181 MHz, which is more than twice as high as previous designs in this technology. This design is first tested in isolation an then combined with our current RISC-V processor specially designed to be used in such a harsh environment. This architecture achieves 146.5 million instructions per second (MIPS), which is four times higher than other off the shelf solution synthesized for the same harsh environment technology.
We present an optimised distributed-memory algorithm for the unpreconditioned conjugate gradient (CG) method. We experiment with using the CG algorithm with the compressed sparse row (CSR), compressed sparse row 5 (CSR5), compressed sparse row 2 (CSR2) and symmetric compressed sparse row (SCSR) sparse matrix formats. For the CG algorithm, we present a CSR5-based and an SCSR-based distributed-memory sparse matrix-vector multiplication (SpMV) algorithm. We developed five distributed-memory CG implementations using different combinations of the mentioned sparse matrix formats and SpMV algorithms. We benchmarked our implementations on a distributed-memory computer cluster with Intel x86-64 CPUs. For the maximum benchmarked number of compute nodes, the median performance of our optimised distributed-memory CG algorithm with CSR-based SpMV was 58
Field-programmable gate arrays (FPGAs) in space applications come with the drawback of radiation effects. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which will operate on the International Space Station (ISS) for several years. A total of more than 100 FPGAs distributed throughout the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. On ISS, radiation effects must be taken into account, the functionality of the electronics must be monitored, and errors must be handled properly. Commercial off-the-shelf (COTS) FPGAs are used, which are not radiation hardened by design. This paper describes the methods and measures used to mitigate the effects of radiation in an application specific COTS-FPGA-based communication network. Based on the firmware for a central communication network switch in BECCAL the steps are described to integrate fault mitigation into the design while optimizing the firmware to stay within the (FPGAs) tight resource constraints. Multiple different redundancy mechanisms are implemented, using VHDL constructs or the Synplify Elite synthesis tool, to select the variant fitting the task best. A redundant integrity checker module is developed that can notify preceding network devices of data and configuration bit errors. The firmware is validated and evaluated by injecting faults into data and configuration registers in simulation and real hardware. For the switch fabric it is shown, that dual modular redundancy (DMR) with error detection is the best strategy for BECCAL. Together with the triple modular redundancy (TMR) protected integrity checker, this combination completely prevents silent data corruptions (SDCs) in the design as shown in simulation and by injecting faults into hardware using the Intel Fault Injection FPGA IP Core while staying within the resource limitation of a low-cost COTS FPGA.
The increasing complexity of high-performance computing (HPC) systems, particularly those utilizing a multi-GPU cluster architecture, presents significant challenges for developers. Low-level, vendor-specific application programming interfaces (APIs) often require deep technical knowledge, complicating maintenance and reducing performance portability. This complexity is exacerbated when large data sizes or bandwidth requirements necessitate data compression. Integrating such end-to-end compression into existing codebases dealing with distributed memory multi-GPU clusters is often labor-intensive and error-prone, particularly when flexibility in the choice of compression algorithm and implementation is desired. In this work, we propose a high-level, user-friendly end-to-end data compression API integrated into the Celerity runtime system, built on the SYCL programming model. By abstracting the complexities of integrating various compression algorithms, we aim to enhance data transfer and storage efficiency, without a large cost in development complexity. Our API supports multiple compression types and memory layouts, enabling developers to leverage compression without extensive modifications to their existing codebases. We evaluate this API and its prototype implementation in various benchmarks, demonstrating its effectiveness in reducing storage and bandwidth requirements, while maintaining high performance.
In this paper, we present a comprehensive study on the parallelization and optimization of Legendre Pairs (LPs) construction using High-Performance Computing (HPC) techniques. We address the computational challenges associated with LPs, particularly for large lengths, and propose a highly effective multi-GPU solution. Throughout this journey, we present our findings, insights, and contributions including the parallelized implementation of LP search using OpenMP, MPI, and CUDA, along with systematic optimization strategies for both CPU and GPU. We demonstrate significant performance improvements, achieving over 6500x and 1900x speedup on NVIDIA H100 and A30 GPUs, respectively, compared to the serial execution on Intel Xeon Gold 6338 CPU.
We present SkePU-Streaming, a two-layer high-level programming framework for specifying complex pipelines composed of portable multi-backend stream processing tasks, each expressed by algorithmic skeletons or user-provided implementations, and its deployment toolchain for distributed heterogeneous parallel systems. Pipeline tasks can have multiple implementation variants to more flexibly exploit the resources of heterogeneous nodes; the convenient expression of multi-variant tasks is achieved by integrating the high-level C++-based skeleton programming framework SkePU with its multiple backends as the main method for portable programming of the stream-processing tasks. Concretely, SkePU-Streaming adds an abstraction layer for pipeline workflow specifications atop SkePU-based task specifications. It extends the SkePU data-container API with stream access operators for use within SkePU and other C++ task code. We present the SkePU-Streaming design and its implementation in a deployment framework for distributed heterogeneous parallel systems, and demonstrate its use with two different video processing applications.
The pre- and exascale computational systems require new programming tools and solutions to develop and deploy applications. Most of them include heterogeneous devices and accelerators. Programming for these platforms generally requires mixing computations programmed using low-level or portability models with partition and communication mechanisms across nodes and devices to overlap computation and communication efficiently. A relevant class of scientific applications that requires this kind of solution to obtain a high degree of scalability are the ISL (Iterative Loop Stencil) applications. EPSILOD is a parallel skeleton for ISL applications targeting heterogeneous distributed systems. In this work, we present an extension of EPSILOD that enables a new range of applications using generic data types, a new domain-specific language for optimized kernel integration, and a new synchronization and communication scheme to increase scalability in Tier-0 computing facilities. We test the new solutions with simple 2D stencils and a 3D Lattice-Boltzmann application. We present an experimental study comparing EPSILOD with a low-level MPI+CUDA code, and with state-of-the-art solutions that simplify the programming in large-scale distributed heterogeneous environments: The Muesli skeleton library and Celerity. The results show that EPSILOD obtains similar or better performance than other solutions in most cases, while reducing the development effort.
FPGAs are promising accelerators for scientific computing tasks because of their potential for delivering high performance-per-Watt. However, programming for optimal performance remains a complex task. Our goal is to bring FPGAs within the reach of domain scientists by developing compilers targeting scientific Fortran code. In this paper, we present a novel approach to aggressively reduce memory utilisation of stencil-based finite-difference Fortran code through a compiler-based automatic program transformation that trades memory accesses for computation. The key contribution of this work is a set of type-driven rewrite rules that identify and eliminate the intermediate arrays in stencil computations and replace them with re-computation, thus reducing the number of memory accesses. The main novelty lies in the transformations to move stencil operations out of maps and folds and to fuse stencils. We demonstrate the effectiveness of our approach using a set of five 3-D and 2-D stencil benchmarks evaluated on an Intel Arria 10 FPGA board. Our transformation result on average in a 2.5× reduction in DRAM usage, a 3.4× increase in DSP usage, and a 25× improvement in throughput. We show on a real-world exemplar, the Large Eddy Simulator for Urban Flows, that our algorithm successfully removes all intermediate arrays (18 in total), reducing the memory footprint by a factor of 4.5× . The memory-reduced FPGA code, automatically transpiled from the original Fortran source, is 9.7× faster than the original Fortran code, and performance competitive with a hand optimised FPGA version while supporting a four times larger domain size.
Modern applications often involve complex, structured or data-parallel computations on large datasets. Traditionally, GPUs have served as the primary accelerators for such tasks, mostly through compute-focused models like CUDA and OpenCL. Vulkan is a more recent cross-platform API, widely adopted for both high-performance graphics and compute. These models require lower-level programming, as developers have to be aware of architectural details; this is not easily accomplished given the dramatic rise in hardware heterogeneity. It has thus become increasingly desirable to adopt higher-level models that abstract away the low-level hardware and API details, and simplify GPU programming. In this paper we present a full-fledged OpenMP translator and runtime offloading infrastructure that targets the Vulkan Compute pipeline. While previous works usually focus on OpenCL or CUDA, this is the first time an OpenMP compiler targets Vulkan shaders. As such, apart from the support for off-the-shelf NVIDIA and AMD GPUs, we are the first to provide OpenMP support for mobile and embedded GPUs, such as VideoCore GPUs. The proposed translator, which is based on an open-source compilation framework, receives standard OpenMP code and converts it to tunable Vulkan shaders. Our approach preserves the simplicity of higher-level programming, while still achieving high performance, as demonstrated by our experimental results.
In distributed systems with redundant network paths, dynamically selecting optimal communication routes for parallel programs is essential for minimizing latency and avoiding congestion. However, this is challenging due to unpredictable network conditions and concurrent workloads that create time-varying performance characteristics. This paper presents a reinforcement learning framework that enables programs to adaptively select communication routes based on historical performance without requiring global network state monitoring. We employ the Upper Confidence Bound 1 (UCB1) algorithm for small candidate sets and an improved ϵ -greedy algorithm for larger sets, providing logarithmic regret bounds in stationary environments and sublinear regret in dynamic scenarios. We demonstrate this approach on the 3-Quads cluster, a distributed system with three redundant subnetworks, where simulation and visualization programs run concurrently. Experiments show that our method reduces data transmission delay by 30-45
Data stream processing (DSP) applications consist of data-flow graphs of operators that process data streams. These operators run as dedicated threads, either in parallel or concurrently, on computing platforms with multi-core CPUs. The decision of where to run threads of parallel programs, specifically which CPU core of the underlying architecture to use, is known as thread pinning, and it can significantly affect the application’s throughput. For DSP applications, finding an efficient pinning can be challenging as it depends on information about the data-flow structure, operator types, and communication patterns. Although thread pinning is a low-level optimization available in several parallel programming frameworks , DSP frameworks typically do not allow users to configure thread pinning, leaving the decision to the Operating System. This paper extends the WindFlow DSP library, and its FastFlow-based parallel runtime system, to expose thread pinning mechanisms through a usable API. The effectiveness of this approach is demonstrated through extensive evaluations of four applications, using six custom pinning strategies on a high-end server.
This paper presents the design of PHI, a modern C++ library that allows for the composable expression of parallel computation patterns. Building upon the principles of GrPPI, PHI introduces a range-like interface that enables for declarative composition of parallel patterns by means of a pipe-like syntax that better aligns with contemporary C++ idioms. Additionally, PHI's architecture aims to separate pattern composition from its execution, allowing for backend-agnostic implementations, and the potential to integrate various execution models.
The rapid expansion of Machine Learning (ML) applications, especially within its subfield of Deep Learning (DL), has created an increasing demand for efficient preprocessing of large tabular datasets that surpass the available memory capacity of single-node systems. This paper introduces a parallel framework, developed as a Python library, designed to efficiently preprocess large-scale tabular datasets for training Deep Neural Networks (DNNs). The library supports various data transformations, including normalization, categorical encoding, and missing value imputation, leveraging parallel computing and chunk-based processing to efficiently handle massive datasets. By distributing preprocessing tasks across multiple cores and facilitating the parallel loading and processing of data chunks without altering the original data file, the proposed library significantly reduces the time required for data preparation, which often represents a critical bottleneck in modern ML pipelines. Experimental evaluation demonstrates substantial performance gains over conventional sequential approaches and state-of-the-art (SOTA) solutions.Furthermore, the library integrates seamlessly with widely adopted DL frameworks, providing a scalable and flexible High-Performance Computing (HPC) tool for data preprocessing in contemporary ML workflows.
To satisfy the growing throughput demand of data-intensive applications, the performance of optical communication systems increased dramatically in recent years. With higher throughput, more advanced equalizers are crucial, to compensate for impairments caused by inter-symbol interference (ISI). The latest research shows that artificial neural network (ANN)-based equalizers are promising candidates to replace traditional algorithms for high-throughput communications. On the other hand, not only throughput but also flexibility is a main objective of beyond-5 G and 6 G communication systems. A platform that is able to satisfy the strict throughput and flexibility requirements of modern communication systems are field programmable gate arrays (FPGAs). Thus, in this work, we present a high-performance FPGA implementation of an ANN-based equalizer, which meets the throughput requirements of modern optical communication systems. Further, our architecture is highly flexible since it includes a variable degree of paralellism (DOP) and therefore can also be applied to low-cost or low-power applications which is demonstrated for a magnetic recording channel. The implementation is based on a cross-layer design approach featuring optimizations from the algorithm down to the hardware architecture, including a detailed quantization analysis. Moreover, we present a framework to reduce the latency of the ANN-based equalizer under given throughput constraints. As a result, the bit error rate (BER) of our equalizer for the optical fiber channel is around four times lower than that of a conventional one, while the corresponding FPGA implementation achieves a throughput of more than 40GBd, outperforming a high-performance graphics processing unit (GPU) by three orders of magnitude for a similar batch size.
