An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.

Electrostatic discharge (ESD) is a major threat to the reliability of integrated circuits, where approximately 20% of total integrated circuit (IC) failures are due to ESD. Discharge of charged objects or human discharge into IC chip pins with very high currents (up to 10 A) in a short time period (1 ns to 200 ns) causes serious damage to the very sensitive devices of the circuitry. This may happened during manufacturing, assembly, shipment, and in the field. Since the phenomenon is unavoidable, there is a strong need of developing proper strategies to protect the functional devices, circuits and systems. In this paper we present the analysis of the ESD protection structure supported by the advanced 2-D mixed mode electro-thermal device and circuit simulation.

In this paper we present an experimental method which modifies the standard single pulse UIS test to multi-pulse UIS test which better corresponds to the real industrial situation where devices have to sustain several consecutive stress pulses. Undamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the ruggedness , which characterizes the device capability to handle high avalanche currents during the applied stress. Additional current source was connected to standard UIS test to evaluate device temperature during and after application of a stress impulse. For better analysis of the internal behaviour of power devices under study a 2-D mixed mode electro-thermal simulations were used for electrophysical interpretation of obtained experimental data.

Boron outdiffusion from the base into the emitter and collector caused by annealing in SiGe heterobipolar transistors (HBTs) has a serious influence on the transit frequency. One solution of the problem of boron outdiffusion is the creation of intrinsic spacers between the base, emitter and collector layers to prevent diffusion of boron across the heterointerface. For optimisation of SiGe HBT properties, several simulators are used. This paper presents a quantitative analysis of a SiGe HBT by process simulators SUPREM IV.GS and ISE TCAD-DIOS. Models for simulation of a boron-doped SiGe base of HBT are discussed and compared.

The diffusion process and its influence on the broadening of the base bounded from both sides by undoped spacer layers of an npn SiGe HBT have been investigated by process simulator JSE TCAD. Boron diffusion into strained SiGe layers was studied for different times of annealing, Ge content in SiGe and widths of undoped spacer layers.

The formerly derived modified method of evaluation of the Schottky barrier height applied on Pt/Au-GaN Schottky structures is presented. It is based on the measurement of I-V characteristics in a wide temperature range. By subtraction of generation-recombination, tunnelling and leakage currents from the total current, the "pure" thermionic emission current I/sub te/ and subsequently Schottky barrier height /spl phi//sub b/ can be evaluated with higher physical relevance. The advantage of the mentioned method is that it allows evaluation of /spl phi//sub b/ from the measured I-V characteristics which significantly deviate from the ideal thermionic-emission characteristics represented in semi-logarithmic coordinates by a straight line. The determination of the Schottky barrier ob on GaN and related compound semiconductors with higher precision is important for further analysis of new combinations of metals and semiconductors and better understanding of the physical behaviour at the interface.