The advanced GaN-based devices utilized for highperformanceradio frequency (RF) applications are intensivelystudied to be used as RF sensors or amplifiers. The paper is focusedon microwave characterization of two port passive devices,especially on-chip calibration structures and InAlGaN/GaNelectron mobility transistor (HEMT) operating in the cold biasregion (zero applied voltage). The acquired S-parameters areinputs to build a passive device small-signal model consisting ofthree star-connected impedances. The calculated Z-parameters arepossible to be utilized for on-chip signal paths design. Theparameters to be calculated are assumed frequency independent,however, more proper HEMT modelling requires non-zero voltageapplication, therefore, the model possibilities are depicted anddiscussed.

The field of high-frequency device research requires the utilization of a vector network analyser and the advanced calibration methods to correct measurement imperfections caused by two RF signal paths, from the signal generator/detector to the probe tips and probe tips to the on-chip device under test (DUT). Plenty of the calibration methods utilizing reference RF devices including robust calculations were already introduced. This paper deals with imperfection correction of the probe tips to the on-chip DUT RF signal path. OPEN, SHORT, THRU on-chip test structures are used together with iteration calculations which allow for a simple implementation into automated calibration process. Vector error correction of s- parameters obtained by calibration process are subsequently employed in de- embedding process to acquire s-parameters of a DUT.

This study presents a thermo-mechanical simulation of a power SiC transistor integrated into a printed circuit board (PCB). The primary objective is to optimize the design to enhance the thermal and mechanical properties of the device. Through numerical simulations, critical areas within systems utilizing power transistors embedded in PCBs are identified and optimized to reduce mechanical strain and improve heat dissipation. These improvements contribute to the overall reliability of the final system.

This paper deals with the defect study of a monolithically integrated GaN power transistor on a conductive Si substrate by Deep Level Transient Fourier Spectroscopy method (DLTFS). Due to the high non-exponentiality of measured capacitance transients we focused only on defects that were determined with high certainty in the investigated samples and confirmed by measurements under different conditions. Parameters of six electrically active defects with activation energies 0.28, 0.53, 0.81, 0.92, 0.09 a 0.84 eV were determined. The origin of these defects probably corresponds to dislocation extended from the GaN separating layer to the AlGaN layer, nitrogen point defects (vacancies and interstitials) or dislocations. We observed that the signal significantly increases in the low-temperature range at positive reverse voltages.

This paper presents the development of a neural network-based approach for the calibration of electrical models of semiconductor devices, focusing on diodes and MOSFET transistors. Extensive datasets from experimental measurements and simulations were utilized to train and validate the models. The calibrated models demonstrated high accuracy and performance across diverse operational conditions, proving the effectiveness of neural networks in automating the calibration process. This research advances the field of semiconductor modelling, with significant potential for application in optimizing device performance.

High-frequency wireless communication in consumer, defense, and space applications heavily relies on the use of compound semiconductor amplifiers. Typically, the X to Ka wireless bands (similar to 8-40 GHz) are covered by GaN and GaAs-based devices, respectively, to the desired output power. GaAs-based high-electron mobility transistors (HEMTs) provide an unprecedented ultralow-noise high-frequency operation even at cryogenic temperatures, critically important for the high-fidelity amplification of weak qubit states in quantum computing. Increased output power from GaAs-based devices while maintaining low self-heating is an important but challenging objective. In this study, we used an epitaxial lift-off (ELO) technique to transfer GaAs nanomembranes onto foreign substrates (sapphire, Si, and SiC) and analyzed the thermal properties of the van der Waals-bonded GaAs films by nanosecond transient thermoreflectance (TTR). Electrothermal simulation of a GaAs HEMT was used to predict the thermal performance of the transferred devices, and a significant decrease of similar to 30% in the device thermal resistance (Rth) was observed when SiC and diamond substrates were used. Our results also predict that the on-state channel temperature rise can be further decreased by similar to 29 to 41% if the GaAs/substrate interface is improved by increased thermal boundary conductance. Our study finds that the ELO-transferred GaAs HEMTs onto foreign highly thermally conductive substrates can significantly improve their thermal performance and allow for higher output while keeping the on-state temperature within the safe operating margin.

To demonstrate the benefits of advanced PCB manufacturing technologies in power electronics, this study presents a PCB embedded SiC half bridge design and compares its switching transients with the conventional SiC package design. The presented PCB embedded design stands out as a compact design, occupying nearly 40 % less space compared to the conventional design. The silver sintered die attached copper lead frame, low thermal resistivity prepreg, and copper filled laser microvias provide an effective thermal conductivity between die and the cooling side of the PCB. The compact design also ensures the power loop inductance below 1.5nH at 1MHz and, compared to conventional SiC package design, offers five times less parasitic PCB capacitance. The experimental results show that the switching speed of the designs are 19 V/ns and 15 V/ns during turn on transients, and 8 V/ns for both during turn off transients. The lower overshoot stress and faster damped ringing in PCB embedded design contribute to the reduction of the switching losses.

A simulation study of the packaging of a power double-diffused metal-oxide-semiconductor (DMOS) transistor is presented. The investigation focuses on refining the design to enhance the device's electrical performance. The simulation findings show that an optimized design can improve the switching speed of the power DMOS transistor. The ribbon-bond source electrode's reduced parasitic inductance and resistance enhance the switching speed of the power DMOS transistor by around 13%.

This paper presents an analysis and design of a power MOSFET transistor embedded in a printed circuit board (PCB). The analysis and design are supported by 3D electro-thermo-mechanical simulations. The analysis is focused on a comparison of the properties of a discrete power MOSFET transistor mounted on the surface of a PCB and a power MOSFET transistor embedded in a PCB. The conventional technology of packaged transistors exhibits significantly higher values of parasitic inductance, resistance, and thermal impedance compared to the embedded technology. 3D numerical finite element method simulations are effectively used for the design and optimization of the embedded technology in order to improve the electrical, thermal, and mechanical reliability performance of the device.

In this article, pinch-off voltage biasing was utilized for the first time to determine the average channel temperature of the AlGaN/GaN HEMT, which made it possible to exclude the device’s electrical parameters dependence in the linear operating mode. The theoretical part is focused on the thermal model with temperature-dependent thermal resistance utilization for active area average temperature determination of the HEMT under quasi-static operation. The experimental part deals with drain-to-source current comparison utilizing quasi-static and pinch-off voltage-biased short-pulse output ${I}$ – ${V}$ characteristics and additional isothermal trapping phenomena determined from the threshold voltage shift. The appropriate use and combination of methods for the active area average temperature determination utilizing constant isothermal saturation current or short-pulse current were discussed.

Herein, vertical GaN transistors with a semi‐insulating (SI) 1.3 μm thick channel layer and C doping of 1 × 10 17 cm −3 are studied. Structures are grown using a metal–organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 μm thick n‐GaN drift layer (Si doping of ≈ 1 × 10 17 cm −3 ) and a top n‐GaN contact layer. A circular mesa region with a diameter of 180 μm is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al 2 O 3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current–voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 10 7 at −2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post‐metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm 2 V −1 s −1 .

This paper introduces the results of the Deep Level Transient Fourier Spectroscopy (DLTFS) study of the defects distribution in power double-trench SiC MOSFETs before and after the applied defined electrical stress. Electrical stress significantly changes the distribution of electrically active defects in temperature ranges from 400 to 500 K. The presence of RD 1/2 , boron impurities, carbon interstitial, Z 1 /Z 2 defect, B and D centre was confirmed. After electrical stress, the most significant defect in the investigated samples was a double defect RD 1/2.

The modified thermal device model was adapted to determine the channel temperature of the AlGaN/GaN HEMT operating under pulsed and quasi-static conditions. The differential analysis of the isothermal and thermal part of the resulting current, as well as ambient temperature variation, is utilized to determine the average channel temperature. Ambient temperature increases in the device operating range is required under low-power operation only, while under high-power operation the thermal stress of the device is significantly reduced due to small ambient temperature variation. In addition, trapping phenomena incorporation is demonstrated to obtain more accurate results utilizing the HEMT threshold voltage shift and transconductance. For experimental verification of the thermal model, Al0.25Ga0.75N/GaN HEMT electrical properties are investigated. Experimentally verified results are in a good agreement with numerical simulations.

This paper presents the characterization and evaluation of current transport properties of power SiC Schottky diode. The evaluation of the main Schottky diode properties is based on the proposed advanced model. This model allows assessing the effect of particular current transport mechanisms with high accuracy. The presence and influence of tunneling current in I-V characteristics are evident, mainly for low temperatures. Unlike previously published results, the proposed model provides a reasonable slight decrease of Schottky barrier height with increasing temperature due to the narrowing of the energy bandgap. The results and model are validated by finite element method (FEM) electrophysical simulations. Evaluated parameters of SiC Schottky diode, such as Schottky barrier height of 1.28 eV and Richardson constant of 1.46 x 10(6) Am-2K-2 are in good agreement with recent research and FEM simulations. (C) 2021 Elsevier Ltd. All rights reserved.

This paper describes a proposed methodology for simulation of thermomechanical properties and reliability of power IGBT devices and modules. This paper consists of an analysis of the results and design optimization of modern IGBT modules and devices with commercial simulation software support. In practice, these simulations can replace expensive and protracted experimental works in an effort to improve thermomechanical parameters, reliability and operating life time of these components.

An optimization of electrical, thermal, and mechanical properties of SiC MOSFET transistors supported by advanced effective 3-D electro-thermal device simulation is presented. The developed simulation method is capable of a full analysis of complex structures with a high speed of simulation and simple implementation. The simulation method is utilized for electrical and thermal analysis of power SiC MOSFET. Two bonding methods of SiC MOSFET transistor are analyzed and compared. Simulation results demonstrated that the optimized clip-bond concept has better electrical and thermal performance than the wire-bond.

The paper presents part of results of double-pulse switching tests and extraction of dynamic on-resistance of packaged normally-off GaN HEMTs. Devices were tested under various switching conditions. Effects of the switching parameters on dynamic on-resistance were analysed and compared. Samples were exposed to repetitive SC stress for several thousand repetitions of switching. Shift of on-resistance due to short-circuit stress was observed, but not of significant magnitude.

This paper investigates the robustness and reliability issues of commercial 1.2-kV 4H-SiC MOSFETs under repetitive unclamped inductive switching (UIS). The degradation of device characteristics, including the transfer characteristics, drain leakage current $I_{dss}$ , and output characteristics, is observed. A significant increase in leakage current was observed after relatively short avalanche stress (UIS stress), and device destruction occurred after 30 million of cycles. Besides the shift of static electrical characteristics, also a change in switching times was observed. The hot carriers injection and trapping into the gate oxide and its interfaces is believed to be responsible for the variation of electrical parameters.

Thermo-mechanical simulation study of a power transistor embedded in a printed circuit board (PCB) is presented. The analysis is focused on the optimization of the design to improve the thermal and mechanical reliability performance of the system. Numerical simulations are effectively used in the identification of critical areas in the systems using power transistors embedded in the PCB, and their optimization with respect to lower mechanical strain and better heat transfer, both leading to improved reliability of the final system.

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance RON , breakdown voltage VBR, threshold voltage VTH , and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance RDSon, where a 14 % increase was observed after 6 · 10 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I − V curves was observed with considerable impact on the RON where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO2 and on interfaces were detected on stressed samples.