This study investigates the influence of post-deposition annealing (PDA) ambient and temperature on atomic layer deposition (ALD)-grown SiO2 and HfO2/SiO2 gate dielectrics for 4H-silicon carbide (SiC) MOS devices. PDAs were conducted in either nitrogen (N2) or forming gas (FG) environments over a temperature range of 600-1100 degrees C. Comprehensive electrical characterization including capacitance-voltage (C-V), current-voltage (I-V), interface trap density (DIT), before implementing optimum PDA conditions in lateral MOSFETs. DIT values as low as similar to 0.8 & times; 1011 cm-2 eV-1 and 0.95 & times; 1011 cm-2 eV-1 for ALD grown SiO2 and HfO2/SiO2 stacks. Lateral MOSFETs with the SiO2-only dielectric layer annealed in FG at 1100 degrees C achieved a field-effect mobility of 33.93 +/- 1.87 cm2/V s. In contrast, the same hydrogen-containing FG anneal had a deleterious effect on the HfO2/SiO2 stacks; instead annealing the HfO2/SiO2 layers in pure N2 at 1100 degrees C resulted in an increased mobility of 43.91 +/- 2.07 cm2/V s. Grazing incidence X-ray diffraction (GI-XRD) confirmed that high-temperature annealing induces crystallization in the HfO2 layer, while the SiO2 layer remains amorphous. These findings emphasize the critical influence of PDA conditions and ambient atmospheres on dielectric quality, interface stability, and overall device performance for SiC-based MOSFETs.

The shape of 4H-silicon carbide mesas after annealing at 1550 degrees C under high-purity argon, hydrogen and hydrogen chloride gas has been examined. While rounding of mesa corners occurs under argon and hydrogen chloride, etching by molecular hydrogen produces a faceted corner shape, with well-defined angles and facet lengths that can be predictably derived from the etching duration. Hydrogen etches mesa sidewalls anisotropically depending on the mesa orientation relative to the substrate crystal, which is prominent after long annealing times. Microtrenches, which occur at the mesa base during plasma etching, were removed inside narrow trenches by all gases examined. The processes presented herein offer a convenient method for tuneable mesa shaping at the sub-micron level, otherwise unattainable by standard lithographic and plasma etching processes, and which are applicable to electronic device fabrication.

We investigate the physical and electrical characteristics of the Al-doped or undoped HfO 2 /SiO 2 gate stacks on 4H-SiC by testing MOSCAP chips fabricated in house. A clear reduction in accumulation capacitance (C ox ) with increasing chuck temperature from room temperature up to 523 K is observed, with Al-doping playing a key role and aligning with temperature-dependent Landau ferroelectric theory. Chips annealed at 1100°C in N₂ ambient show the highest C ox decrease rates while maintaining functional MOS interfaces with acceptable flatband voltage, hysteresis, and Dit profiles. TCAD simulations on a double trench MOSFET model, based on the extracted data indicate improved electro-thermal performance, demonstrating that Al-doped HfO₂/SiO₂ gate stacks are a promising approach for enhancing 4H-SiC power devices.

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (RDS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in RDS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in RDS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs.

This study investigates the static and Short-Circuit performance of a 3.3 kV semi-Superjunction (SJ) MOSFET using TCAD simulations, benchmarked against a fabricated conventional planar MOSFET. The proposed design is based on the cost-effective trench etching and side-wall implantation fabrication method. The analysis demonstrates a wide implantation window, defined by SC withstand time (SCWT) and maximum blocking voltage (BV) performance. Compared to the fabricated MOSFET, the proposed semi-SJ design achieves a 22% improvement in on-state resistance (Ron) and an 11% increase in maximum BV.

A challenge in the development of Silicon carbide (SiC) gate turn-off thyristors lie in an uneven transient behaviour, necessitating expensive snubbers. To address these limitations and simplify circuit topology we present an optimized 16 kV n-type SiC integrated gate commutated thyristor (IGCT) design, which utilises a novel highly doped base strip (HDBS). A particular focus is on optimizing the gate commutation of the GCT during switching, and the trade-offs in the HDBS base design were investigated. The findings reveal that compared with conventional GCT design, the HDBS design under high current conditions recorded a 11.8% reduction in turn-off power losses. When simulating the device in a high-voltage scenario, the HDBS IGCT demonstrated a 3.9% reduction in turn-off power losses and an improved turn-on power loss performance. This resulted in a reduction of power losses by 12.1% and 2.3% in high current and high voltage conditions, respectively. In summary, the novel SiC HDBS IGCT design paves the way towards a secure, high current density, and low loss switching SiC thyristor device.

The 4H-SiC MOSFET is emerging as a superior alternative to Si IGBT technology, particularly with advancements in new trench device generations. This work investigates the technology limitations and trade-offs of the fourth-generation Rohm double trench MOSFET, benchmarking it against data-sheet characteristics using a TCAD software. As SiC technology matures, fabrication and processing techniques improve. Simulated ultra-low resistance substrates (2.5 mΩ·cm) and reduced interface trap densities (μCH - 117 cm2/V·s) combined, resulted in on-state improvement of 28.3 %. While various methods exist to enhance device performance through cell design and optimization, this study investigates the static and dynamic characteristics of the double-trench MOSFET with multiple active trenches. The analysis showed that with a 6.9 % improvement in on-state resistance, comparable short-circuit and off-state performance can be achieved. These findings provide valuable insights into optimizing trench MOSFET designs and their trade-off space.

A 1.2 kV lateral RESURF Schottky diode (TZ-SBD) have been designed from SZ-SBD that can recover from a single-event effect (SEE) in which a heavy ion traverses the device at a linear energy transfer (LET) of 60 MeV·cm²/mg, ESA’s standard. Compared to SZ-SBD, TZ-SBD has an additional split in the N-drift region which is usually used to improve the electric field distribution so its breakdown voltage is improved by 9%. During the single events simulations, the maximum temperature is 919 K with reverse voltage (VR) = 1200 V and LET = 60 MeV·cm²/mg, which is much lower then the SiC melting temperature (3100 K) and the chemically unstable temperature of SiC in the presence of metal (1073 K).

A Post-deposition annealing (PDA) study on atomic layer deposited (ALD)-SiO2/4H-SiC Metal-oxide semiconductor capacitors (MOSCAPs) is presented in this paper. This paper reports that varying the annealing time in conventional PDA (in Nitrous oxide or forming gas) and in forming gas rapid thermal annealing (RTA) PDA does not affect the electrical parameters of the MOS interface. Varying the annealing temperature for forming gas quartz PDA does not affect the electrical parameters either. Flatband voltage, hysteresis, and frequency dispersion of the MOS interface individually all had a positive correlation against the temperature ramp rate, while the annealing time and temperature were kept constant. This result subsequently led to a thermal budget investigation of all PDAs, revealing that thermal budget affects the flatband voltage and hysteresis of the SiO 2 /4H-SiC MOS interface.

This study describes the design and optimization of a 3.3 kV silicon carbide (SiC) semi-super junction(semi-SJ) Schottky barrier diode (SBD). The proposed structure features a 7 mu m deep trench filled with silicon dioxide (SiO2). Aluminum (Al+) sidewall implants are carried out, which help to form a charge balance region. The ON-state improvement of the proposed semi-SJ structure is 16.2%, compared to a planar diode. This results in a specific ON-state resistance (R-ON,R-SP) of 6.2 mcm(2), which surpasses the unipolar limit. The article also addresses the issue of poor blocking voltage performance associated with conventional termination techniques. To mitigate this problem, novel termination designs, which incorporate double-zone junction termination extension (DJTE) and optimally placed rings, are proposed and verified through technology computer-aided design (TCAD) simulations. The most promising structure allows, for the first time, for both a wide implantation window and a high breakdown voltage, reaching 98.3% (4365 V) of the ideal active cell breakdown.

In recent years, silicon carbide (SiC) based devices are increasingly replacing their silicon counterparts in power conversion applications due to their performance superiority. SiC insulated-gate bipolar transistors are particularly interesting as they appear to be the most appropriate for medium and high voltage applications due to their low on-state voltage drop for devices rated at 10kV or higher. However, the widespread adoption of SiC IGBT requires rugged devices capable of surviving in harsh conditions. By using Sentaurus TCAD and validated models based on published experimental results, the short-circuit, unintentional turn-on and dV/dt ruggedness of SiC IGBTs are comprehensively explored and the impact of device parameters on the overall IGBT ruggedness were identified. This paper aims to propose the most efficient methods for IGBT ruggedness enhancement on the device level.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are successfully replacing traditional silicon insulated gate bipolar transistors (Si IGBTs) in power applications. Nonetheless, two crucial challenges persist: gate-oxide reliability and a reduced short circuit (SC) withstand time. This paper explores a novel MOSFET structure, which is designed to address these concerns and compares it with existing designs through extensive 3D TCAD simulations. The proposed MOSFET structure features a p-region under the gate, providing a unique configuration for improved performance during SC events. This novel structure is then compared to two commercially realized MOSFET structures. Our structure has a superior on-state performance with a specific resistance of 1.48 mΩ /cm2, showing an improvement by 25 % and 15 %, respectively. It also increases the blocking capability by 100 V and SC withstand time in comparison to the double-trench MOSFET.

Trench epitaxy of 4H-SiC is investigated with the supersaturation of chlorinated chemistry at a growth temperature of 1550 °C. Coupled with a lower growth temperature than has been previously reported, the integrity of the 4H-SiC trenches is retained and minimal rounding effects of H2 annealing prior to growth are observed. The system gives different growth rates of materials on the various crystal faces of the trenches and can be used to improve the refilling process, resulting in the reduced void formation. The addition of excessive levels of HCl can suppress trench epitaxy by reducing the growth rate on the sidewalls of trenches in favor of growth on the surface. The processes demonstrated offer a scalable and reproducible method to fabricate SiC-based superjunction device structures for applications in high voltage power electronics.

Silicon carbide (SiC) based power devices are highly competitive and widely used, especially in the electric vehicle (EV) market. Beyond the "conventional" 650-1700 V blocking voltage space for EV applications, high-voltage (>3 kV), high-current (>100 A) devices have raised commercial interest for traction and PV applications. The fundamental advantages of the Superjunction (SJ) concept are of particular interest to help reduce the drift region resistance. The proposed 3.3 kV semi-SJ Schottky diode reduces the R-ON,R-SP by 9.7 %, compared to a planar diode solution. Additionally, with the introduction of a novel etched termination (ET) combined with junction termination extension (JTE) and floating field rings (FFR) blocking is improved by 6 %.

For a power device to be used in space, it must be able to recover from a single event effect caused by heavy ion radiation. Conventional vertical silicon carbide (SiC) power devices such as automotive diodes and MOSFETs, can only meet this requirement if they are heavily derated, a 1200 V device typically unusable above 200 V. In this paper, a lateral RESURF Schottky diode has been designed in TCAD simulation using a radiation-hard (rad-hard) by design methodology. By preventing anode-to-cathode shorting that occurs in a vertical drift region, the lateral design is shown to recover after a heavy ion traverses the device with a linear energy transfer (LET) of 60 MeV·cm2/mg, while the device is blocking 1200 V. The design splits the drift region into a higher doping zone closer to the cathode (Zone 2) of 1.5×1017 cm−3 and a lower doping zone closer to the anode (Zone 1) of 1×1016 cm−3. The electric field spikes were reduced while the device was recovering. This design keeps the local temperature in the device to under 1000 K if the heavy ion penetrates the device in a direction perpendicular to the surface. Other entry positions and directions are also simulated and a maximum temperature of 1733 K occurs when the ion path is horizontal, entering at 1 μm below the surface. However, this temperature peak occurs at the cathode, which is not expected to lead to lasting leakage damage. A deep P+ pillar embedded into the anode acts as a collector for holes generated during the single event. Simulations show that a deeper P+ pillar, to a depth of up to 5 μm, reduces the hole density in the N-drift region and P-epi layer during recovery. This also allows the Zone 1 doping to be increased to as much as 5×1016 cm−3, thereby reducing on-state losses.

Inherent symmetry breaking at the interface has been fundamental to a myriad of physical effects and functionalities, such as efficient spin–charge interconversion, exotic magnetic structures and an emergent bulk photovoltaic effect. It has recently been demonstrated that interface asymmetry can induce sizable piezoelectric effects in heterostructures, even those consisting of centrosymmetric semiconductors, which provides flexibility to develop and optimize electromechanical coupling phenomena. Here, by targeted engineering of the interface symmetry, we achieve piezoelectric phenomena behaving as the electrical analogue of the negative Poisson’s ratio. This effect, termed the auxetic piezoelectric effect, exhibits the same sign for the longitudinal ( d 33 ) and transverse ( d 31 , d 32 ) piezoelectric coefficients, enabling a simultaneous contraction or expansion in all directions under an external electrical stimulus. The signs of the transverse coefficients can be further tuned via in-plane symmetry anisotropy. The effects exist in a wide range of material systems and exhibit substantial coefficients, indicating potential implications for all-semiconductor actuator, sensor and filter applications.

We demonstrate the growth of 3C-SiC with reduced planar defects on a micro-scale compliant substrate. Heteroepitaxial growth of 3C-SiC on trenches with a width and separation of 2 µm, etched into a Si(001) substrate, is found to suppress defect propagation through the epilayer. Stacking faults and other planar defects are channeled away from the center of the patterned structures, which are rounded through the use of H2 annealing at 1100 °C. Void formation between the columns of 3C-SiC growth acts as a termination point for defects, and coalescence of these columns into a continuous epilayer is promoted through the addition of HCl in the growth phase. The process of fabricating these compliant substrates utilizes standard processing techniques found within the semiconductor industry and is independent of the substrate orientation and offcut.

The total ionising dose (TID) reliability of a phosphorous pentoxide (P2O5) treated SiO2 (silicon dioxide) layer is compared for the first time to other industrially relevant oxides formed on 4H-silicon carbide (SiC). Metal-oxide-semiconductor capacitors (MOSCAPs) are characterised before and after irradiation to ascertain changes in flat band voltage shift, leakage current, and dielectric breakdown (BV). Secondary ion mass spectrometry (SIMS) profiling reveals a significant phosphorus concentration near the SiO2/SiC interface, which led to improved TID resistance. The P2O5 treated oxide had the lowest leakage current at high voltage bias due to the high-temperature (1,000°C) anneal, though it had a significantly negative flat band voltage due to the high concentration of deposited phosphorus atoms. The thermal and P2O5 oxides demonstrated a TID resistance, suffering only minor shifts in flat band voltage, while the P2O5 oxide suffered the smallest decrease in its BV and the smallest leakage current rise, post-irradiation.

The memory effect of Al doping in 3C-SiC prevents sharp interfaces between layers of different doping levels and can lead to unintentional doping of subsequent epilayers and even growth runs. Introducing HCl into the growth phase of 3C-SiC reduces the Al incorporation but has a significant impact on Al dopant decay rates and background levels within the chamber, resulting in far sharper doping profiles. The impact of relatively high flow rates of HCl is low within a chlorine-based growth system giving fine control over its influence on the growth process and memory effect.