We report an assured way of forming epitaxial CoSi/sub 2/ films on (001) SOI Si substrates when Co is inexhaustible. This is to use bimetallic CoSi/Ti source materials. For the more commonly used Co/Ti source material, epitaxial CoSi/sub 2/ film forms before the Si layer is fully consumed. After the SOI Si has been fully consumed, however, pre-formed epitaxial CoSi/sub 2/ reverted back to polycrystalline CoSi, leading to a dramatic sheet resistance increase. This phase reversal phenomenon arises because in using atomic Co as source material, the Gibbs free energy reduction in forming the CoSi and CoSi/sub 2/ phases is not too different and consequently CoSi becomes the energetically favorable end phase when Co is still available after all Si atoms have been consumed. In using CoSi as the Co source material, the only energetically favorable reaction is to form CoSi/sub 2/.<>

Under the condition of excess metal deposition, the formation of Co and Ti silicides on (001) silicon-on-insulator (SOI) substrates was investigated. In the Co silicide case, a high-resistivity Co silicide film was formed after a high temperature anneal (100 °C for 30 s). Transmission electron microscopy (TEM) revealed that the phase formed was CoSi. The phenomenon of CoSi being the most stable phase, instead of CoSi2, at high temperatures can be understood from both kinetics and thermodynamics. In the Ti silicide case, the most dominant phase was C49-TiSi2, therefore the film resistance was high even after high temperature annealing (900 °C for 20 s). The film morphology was thermally stable on further annealing and the resistance decreased gradually by means of partial transformation of C49-TiSi2 to the C54-TiSi2 phase. For device applications, high resistance silicide films are not desirable, therefore the metal thickness and consequent silicide thickness have to be controlled precisely.

This paper compares the materials and device issues associated with two alternative techniques for the formation of ultrashallow junctions: 1) the use of preamorphization and low energy dopant implantation, combined with rapid, low-temperature annealing; and 2) the use of metal suicides as a diffusion source (SADS) where dopants are implanted into CoSi2 and subsequently diffused into silicon. For conventionally-formed, ultrashallow junctions, preamorphization with either silicon or germanium does not result in shallower junctions. The enhanced diffusion associated with the preamorphization implant damage compensates for the reduction in channeling. Preamorphization does, however, give low sheet resistance junctions and high dopant activation after recrystallization at 550°C. Considerable dopant motion (∼ 50 nm) is observed in the tail region, near the junction, after 10 s of annealing at a relatively low temperature (800°C). The SADS process is seen to produce low leakage n+ and p+ diodes with less than 10 nm of dopant diffusion beyond the silicide/silicon interface, using a very low thermal budget process. By confining the implantation to within the suicide, no crystal defects are created in the underlying silicon. With the SADS process, the limitation on scaling the junction depth lies in producing thin, stable suicide films. Agglomeration of the silicide and pullback along feature edges restrict the maximum thermal cycle and the minimum allowable film thickness.

We have studied the CoSi and CoSi2 phase formation sequence in (001) bulk and SOI Si wafers, using Co/Ti bimetallic layers as source materials which are suitable for growing epitaxial CoSi2 films on (001) Si. In bulk Si, co-formation of polycrystalline CoSi and epitaxial CoSi2 phases at T>500°C have been observed. These phases form respectively at the metal and Si sides of the film. For very long times and/or at high temperatures, only epitaxial CoSi2 is observed, e.g., for samples annealed at 560°C for 30 min or at 900°C for 10 s. When using (001) SOI Si with inexhaustible Co supply, only polycrystalline CoSi has been formed for a 900°C 10 s annealing, which is in contrast to the bulk Si results. This phenomenon is understood on the basis of Gibbs free energy reduction in forming the two phases. In the CoSi2 formation temperature range, Gibbs free energy release in forming CoSi2 is only ~10% more than that of forming CoSi. Consequently, after all Si atoms have been consumed, the formation of CoSi becomes energetically more favorable, since the free energy reduction due to formation of 2x mole of CoSi is much larger than that due to formation of 1x mole of CoSi2, where x is the SOI Si mole number.

Arsenic diffusion and segregation properties at the interface of the epitaxial CoSi2 and Si substrate have been studied. Samples have been prepared using Co-Ti bimetallic source materials and two types of (001) Si substrates: n+ (doped by As to ~2 × 1019 cm−3) and p. For the n+ Si cases, the lower limit of the CoSi2 film formation temperature is increased by ~200°C to ~700°C. SIMS results showed As segregation into Si. For epitaxial CoSi2 film formation at 900°C, the As concentration has increased by a factor of ~2 within a distance of ~30nm from the interface, while the incorporated As in the film is ~30-50 times less than that in Si. For p-type Si substrate cases, the epitaxial CoSi2 film was first grown and followed by As+ implantation (into the film) and drive-in processes. It is observed that As was segregated to the CoSi2-Si interface and diffused into Si. This is in qualitative agreement with our results obtained from the n+ substrate experiments and the results of other authors involving the use of polycrystalline CoSi2 films. In the present cases, all implanted As were conserved at a drive in-temperature of 1000°C for up to 100 s. This is in contrast to the polycrystalline CoSi2 film results which involve a substantial As loss to the film free surfaces. The physical reasons of this difference have been discussed.

The thermal stability of thin CoSi2 submicrometer lines on Si substrate was investigated using electrical evaluation, in situ transmission electron microscopy observations, Rutherford backscattering, and scanning electron microscopy measurements. Heat-treatments were performed at temperatures ranging from 800-degrees-C up to 1100-degrees-C for 10 s in N2 or Ar ambients. It was found that as-formed silicide was thinner at the edges of features giving rise to an apparent difference between the electrically equivalent line width and its physical size. The approximately 45 nm silicide films started to degrade above 1000-degrees-C. Arsenic implantation into the silicide exacerbated its degradation at high temperatures, which resulted in an apparent higher sheet resistance. Narrower lines exhibited a greater relative degradation in resistance than wider ones, and the electrically measured line width decreased after annealing. However, no line width dependence of this line width reduction was observed up to 1000-degrees-C for line widths down to 0.45 mum. Pull back of CoSi2 from the edges of submicrometer lines and the formation of islands were observed after annealing at 1000-degrees-C for about 300 s. A model was proposed to explain the degradation of submicrometer lines Of CoSi2 based on the observed thinner edge phenomenon.

The mechanism of formation of epitaxial CoSi2 film on (001) Si substrate, produced using sequentially deposited Ti-Co bimetallic layer source materials for which Ti was deposited onto the Si substrates first, has been studied by observing the Co silicide formation processes and structures in samples prepared by isochronal annealing and by isothermal annealing. The results demonstrated that, in leading to epitaxial CoSi2 film formation, Ti has played two roles. It has served as a barrier material to Co atoms and thus preventing Co2Si from forming. More importantly, it has allowed nucleation and growth of epitaxial-CoSi2 to dominate the Co silicide film formation process, apparently because it has served as a cleanser to remove native oxide from the Si substrate surface.

The advantages and issues associated with the incorporation of metal silicides and the selective deposition of refractory metals into VLSI device technology are illustrated using examples from 1 to 0.25 μm CMOS technology where the silicide or metal are formed over a pre-existing junction. While the drive current characteristics, latch-up resistance, and series resistance of junction-clad devices ae generally improved, other characteristics, such as hot electron stability, threshold voltage control, and short channel effect may be adversely effected. Reducing the metal (silicide) thickness to reduce silicon consumption and thereby allow scaling the junction depth results in films having considerably higher resistivity and poorer thermal stability. The use of silicide as a diffusion source is shown to be one possible way to scale the technology to smaller dimensions while minimizing the scaling of the silicide thickness. Here we report low leakage (<10 nA/cm2)n+ and p+ junctions where the junction motion beyond the silicide is believed to be less than 1 nm.

We have investigated the formation of TiSi2 and CoSi2 thin films on Si(100) substrates using laser (wave length 248 nm, pulse duration 40 ns and repetition rate 5 Hz) physical vapor deposition (LPVD). The films were deposited from solid targets of TiSi2 and CoSi2 in vacuum with the substrate temperature optimized at 600° C. The films were characterized using x-ray diffraction, scanning electron microscopy (SEM), transmission electron microscopy (TEM) and four point probe ac resistivity. The films were found to be polycrystalline with a texture. The room temperature resistivity was found to be 16 μΩ-@#@ cm and 23 μΩ-cm for TiSi2 and CoSi2 films, respectively. We optimized the processing parameters so as to get particulate free surface. TEM results show that the silicide/silicon interface is quite smooth and there is no perceptible interdiffusion across the interface.

In a previous study it was found that when p‐type (100) silicon wafers in a fused quartz wafer carrier were annealed in argon in the temperature range 900°–1150°C, migrated over the Si wafer surface and etched it. In this initial study, experiments were isochronal, so that different degrees of etching occurred at each temperature studied. In the present study, the heat‐treatments were conducted in a high purity argon atmosphere for periods of time so chosen that at each temperature an approximately equal weight loss of silicon, due to the etching process, could be expected. The effects of heat‐treatment on the resulting surface morphology of etch structures of (100), (110), or (111) silicon wafers were compared. It was found under these equal weight loss conditions that the etching at is anisotropic (polyhedron etch pits are observed) while at higher temperatures a close to isotropic behavior is observed. It is believed that the crystallographic etch structure generation in the anisotropic etching regime begins at crystal lattice defect sites or at impurity inhomogeneities. In addition to the crystallographic etch pit structures, there is observed at very high magnifications, 9000 times, a slight background structure in the anisotropic etching regime. Here, it is believed that this background structure is the beginning of crystallographically defined etch pits, originating again at some sort of crystal defect. In the isotropic regime, where a similar background structure is also observed, but where crystallographic etch pits are not, it is believed that this again represents crystal defects or impurity inhomogeneities being etched at different rates than the lattice planes, but where lattice plane confinement can no longer take place. It is proposed that the transition from the anisotropic to isotropic surface etching is related to the etching rates for different crystallographic orientations becoming essentially equal at higher temperatures. The technique of high temperature annealing in an inert gas atmosphere appears to represent a sensitive way of revealing defects and impurity distribution in crystalline silicon.

Studies of the annealing behavior of (100) silicon wafers in argon in the temperature interval 900°–1150°C indicate that "thermal etching" of silicon is not due to either evaporation of silicon, or reaction with gas‐phase contaminant species, as has been proposed. Instead, it appears due to the reaction of silicon with the fused silica wafer carrier, the silica creeping over the wafer surface, and reacting with it. In a series of vertically stacked wafers arrayed perpendicularly to the gas stream flow direction, the furthermost upstream wafer exhibits the greatest degree of thermal etching because the surrounding gas contains the smallest concentration of . The latter is present as a consequence of the reaction between Si and . The furthermost downstream wafer exhibits the least amount of thermal etching, because the gas surrounding it has become saturated with during its passage over the wafer array. The increased gas‐phase concentration of retards further reaction of the downstream wafers with the fused silica wafer carrier. The thermal etching behavior is highly anisotropic at 1000°C, becoming much less so at 1100°C and above. In a carrier, the thermal etching is reduced dramatically.

The residual extended defects due to end-of-range ion implantation damage can be totally eliminated by Ti silicidation. Shallow p+ junctions were formed by amorphizing the silicon with Ge implantation (85 keV, 1×1015 cm−2) prior to implanting boron (85 keV, 1×1015 cm−2), recrystallizing the amorphous region at 550 °C, and then rapid thermal annealing at 1050 °C for 10 s. A buried sheet of interstitial dislocation loops lying below the surface remained. However, following a self-aligned Ti silicide process, the end-of-range defects due to Ge ion implantation damage were no longer observed in cross-sectional transmission electron micrographs. The annihilation of these end-of-range interstitial dislocation loops is attributed to the injection of vacancies during Ti silicidation.