Direct-bonded heterogeneous integration (DBHi) is a unique chiplet packaging technology using directly-bonded silicon bridges as high-density inter-chip connections. In this paper, we present the reliability results of the DBHi packages on standard laminate substrates without cavity or recess structures. The DBHi modules passed over 2000 cycles of thermal cycling test on JEDEC condition-G (-40~125°C). The selection of the encapsulant for micro joints with the right balance of flowability and joint protectability was the key for the excellent reliability performance. We also demonstrate the scalability to quad chip module (QCM) with silicon bridge chips comprising 30 µm-pitch solder joints. Furthermore, we confirmed the wafer probing test adaptability of the DBHi main chip wafer for mixed-pitch and mixed-height bumps/pads for known-good-dies (KGD) identification which is a key enabler for manufacturing of advanced packaging.

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally, several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar structures and seed layers is investigated. Results from the study highlight potential methods to extend bath life while maintaining photoresist stripping efficiency.

Silicon (Si) handle technology benefits that support advanced chiplet technology applications include: (1) semiconductor process and equipment compatibility, (2) improvement on heating/cooling rates with reduced stress and wafer warpage and (3) contamination avoidance. This paper reports the next generation Infrared (IR) laser debonding technology to release Si handler from 300mm advanced CMOS nodes wafer with or without TSVs. IR laser systems with Gaussian and Top-Hat beam profiles were used to study the laser ablation characteristics on different families of release layers and bonding adhesives. Post wafer debonding, a wafer cleaning process was developed, and the IR laser impacts on passive and active device wafers were studied with physical and electrical tests. The results indicated the optimization of physical structures and IR laser control parameters were critical to achieve quality release for chemical stripping and compatibility with subsequent integration. This IR laser debonding technology continues to successfully support ongoing 2.XD and 3D fine pitch I/O chiplet test vehicle build and integration demonstrations with micropillar solder bonding or Cu-Cu / ILD Hybrid bonding.

In this work, a panel packaging approach based on programmable laser milling, injection molded soldering (IMS), and temporary handling technologies has been proposed and demonstrated for micro thin-film-battery (TFB) cells. Micro TFB cells in the dimensions of 2.5mm × 2.5mm × 0.1mm have been successfully packaged and sealed with overmolding solder.

In this work, a novel packaging structure has been demonstrated for micro-TFB cells. Various semiconductor fabrication and assembly processes have been applied to thin substrate via formation and sealing, micro-TFB singulation and handling, as well as metallic sealing for hermetic battery packaging. Micro-TFB cells in the dimensions of 2.5mm x 2.5mm x 0.1mm have been fabricated and tested. A normalized capacity of similar to 190 pAh/cm(2) has been demonstrated.

Innovations in healthcare, diagnostics, sensors and data analysis with Artificial Intelligence (AI) learning / recommendations offer opportunities for improved personalized healthcare, lower costs and benefits to the medical industry. The age of personalized human health monitoring has begun. Human health monitoring using fluidic diagnostic monitoring, non-invasive sensors, wearables (electronic health sensors), implanted health sensors, sound, visual images, and combinations of these data trends offer individuals personalized healthcare guidance. The data, analytics and recommendations from these personalized solutions are beginning to aide our early detection and understanding of health risks from chronic diseases and overall health / wellness. Examples include: cardiovascular disease, diabetes, oncology / cancer, kidney disease, elder care, Parkinson / Huntington Diseases, and many other healthcare applications. Rapid advancements of innovative healthcare diagnostic tools, health and environmental sensors along with data trending and analysis using AI systems or platforms can provide industry disruptions in healthcare. AI systems already aid health professionals and individuals with knowledge and recommendations that offer the promise of improved quality of life and lower healthcare costs. Examples such as: (1) earlier chronic disease detection and potential for disease progression delay or prevention, (2) understanding individual behavior, medication treatments and effectiveness of the treatments on activities of daily living and (3) personalized care based on your DNA, medical diagnostics and your healthcare trends relative to your healthcare needs and options to manage your quality of life. In this paper, we describe both new technologies and advancements to heterogeneous integration technology tools, materials and processes that provide differentiating electronics for future healthcare diagnostic tools and sensors. These new technologies are being applied to targeted applications in healthcare diagnostics and sensor monitoring for precision diagnostic data, smaller product size and much lower costs. Data streams can leverage AI to provide smart personalized healthcare guidance or solutions that compliment existing technology and data to partners such as healthcare professionals, patients and clients. In many applications, we leverage industry available technology or benefit from these new technology advancements to provide for the best system solution. Examples of these new and advancing technologies include: (1) Precision handling thinned wafers with large die, small die, multi-die, sub-components, components and substrates technologies, (2) Injection molded solder (IMS) technology for wafers (TSV and / or interconnection) and substrates, (3) Precision micro-component, die, multi-die substrate and multi-component assembly / integration technology for healthcare, IoT and AI Systems, (4) Precision laser micro-machining, cutting and welding technology, (5) Flexible multi-channel, micro-fluidic systems for smart sensing, point of care (POC) diagnostics, and AI and (6) Small form factor micro-systems and energy solutions / technologies that support future healthcare, IoT, and AI linked computing solutions. Examples of key challenges and advantages of these technologies for the targeted applications are shared relative to current industry standard solutions. Highlights on future demonstrations in progress at the time of writing this paper are targeted for our 2018 ECTC presentation and other future technical publications.

This paper proposed a high-speed precision handling technology of micro-chip using programmable laser debonding technology for fan-out wafer level packaging (FOWLP) application, and investigated the programmable capability, the speed and the accuracy with laser debonding experiments on chips down to 25umX25um. The proposed FOWLP approach has features of: (a) all steps are based on wafer-level processes by using programmable laser debonding technology to achieve the reconstituted wafer, enabling high-speed precision hanldinghandling technology for micro-chip. And, (b) two bonding interface layers, one high-strength adhesive layer for chips firmly joined to handler and the other UV-sensitive layer for easily laser debonding, can improve the die-shift issues. The successfully debonding results, including selectively debonding 200umX400um chips from handler wafer and specifically debonding 25umX25um chips forming the letters "IBM", indicates the programmable capability of this technology. The experiment results show that the debonding speed can be up to 360,000 components per hour (cph), and the debonding accuracy can be in the microns range.

In this paper we present a novel approach to addressing the challenges of integrating embedded cooling into 3D chip stacks with multiple large high power die layers. 3D chip stacks require the integration of through silicon vias (TSVs) in the active device die layers, with demonstrated reliable production capable processes limiting the height of such vias (and thus the active device die thickness) to approximately 50 micrometers for integrated copper vias, creating constraints on channel height. Limited channel height capability constrains the power which can be transferred to the coolant at reasonable coolant pressure drops. An ideal solution to integrating embedded cooling into a stack of large high power dies would allow higher channel height and require no additional processing of the active dies. In this work we describe and provide initial experimental results for an approach that meets this ideal. In this approach a separate interconnect/channel defining structure is created utilizing a die thinned to a thickness compatible with TSV processes that do not require active device integration. Reliable TSV heights of 100 micrometers or more are obtainable when integration with fine wiring or active devices is not required on either end of the TSV. The thinned die is attached to a handler wafer utilizing a blanket adhesive process. TSV structures along with endpoint metallurgies (pads, solder bumps, etc) are created in the thinned die either before or after thinning and handler attach, depending on the exact TSV and endpoint metallurgy processes chosen. Pillar and/or channel wall structures are lithographically laid out to incorporate the TSVs. The die area outside these pillar/wall structures is completely etched away with a Deep Reactive Ion Etch (RIE) process, leaving an array of fully separated pillar/wall structures attached to the handler wafer. This wafer may, if desired, then be diced into active-die sized arrays. These structures are now attached to receiving pads/solder bumps on one active die or wafer. The handler wafer/die is then released from the structures, leaving them standing attached to the active die or wafer. Finally a second active die or wafer is attached to the other end of the structures, creating coolant channels with embedded TSVs. The process can be repeated with an arbitrary number of active die/interconnect array pairs. The initial experimental work presented here demonstrates this process without integrated TSV's, showing that it is possible to create such structures, attach them to a die, release the handler, and attach a die to the other end of the structures thus creating coolant channels or cavities. This approach and initial demonstration show the potential for reliable high power 3D integration of embedded cooling using active dies incorporating demonstrated TSV processes

This paper reports on a feasibility study of using infrared (IR) laser ablation for silicon handler debonding for the first time. Various lasers were evaluated for the transmission through a Si handler and several release layers were studied for on low-power laser ablation. Debonding of silicon handler has been successfully demonstrated. Furthermore, a test vehicle based on through-silicon-via (TSV) wafers was used to evaluate the impact of IR laser ablation on the devices. Promising electrical testing results are obtained and fast debonding at wafer level has been demonstrated.

This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip cooling. A thermal demonstration vehicle (TDV) has been designed, fabricated and assembled. Radial micro-channels based on deep Si etching was integrated with a manifold chip to form a 2-layer chip stack, which has been assembled using a ceramic substrate and a Cu manifold. A test vehicle with an effective critical heat flux of 340 W/cm2 and uniform cooling has been successfully demonstrated using a dielectric coolant (R1234ze).

In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with “flat” metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten solder (IMS) processes. The pre-stacked chips are then assembled and packaged on the bumped laminates successfully.