We describe work that extends three-dimensional (3-D) patterned overlay high-density interconnect (HDI) to high-performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (>90%) optical fill factor, high quantum efficiency, 200-ns inter-frame time interval, and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 160 channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. A novel 3-D integrated sensor-electronics (mirror-cube) imager architecture is proposed. We also briefly review progress in the custom fast image-processing electronics.

We describe work that extends 3-D patterned overlay high-density interconnect (HDI) to high performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (>90%) optical fill factor, high quantum efficiency, 200 ns inter-frame time interval and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 160-channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. We also briefly review progress in the custom fast image-processing electronics.

Array sensors (e.g. focal plane array detectors) have densely aggregated cells to capture low energy levels that are converted into electrical signals. In hybrid assemblies, where focal plane arrays are bump-bonded to readout ICs, pixel density is being continually increased as processing and assembly technologies improve. Denser arrays, combined with extremely high frame rates (e.g. >106 frames/sec) create a formidable explosion in signal content. One approach to overcoming this issue is to move the signal processing closer to the array, minimizing the number of interconnects and the interconnect length the raw pixel signal outputs must travel prior to digitization, providing opportunity to buffer bursts (<64 frames) of high-rate collection sessions. One innovative approach to achieving this is to use 3D stacking of the pre-processing electronics for each pixel row directly behind the sensor array. This paper describes the development of a high density, 3D stacking technology that is being applied to an 8000-pixel array sensor cube that can eventually be scaled to mega-pixel densities through tiling.

Array sensors such as Focal Plane Array Detectors, IR Imagers, X-Ray detectors and the like, have dense arrays of detector cells that capture ultra-low levels of energy. The energy received in each array pixel is in the form of low levels of UV, IR, or visible light, X-Rays, microwaves or other electromagnetic energy and is converted in each array pixel into electrical signals. These sensor arrays are used in military imaging or detection or in medical or industrial diagnostic imagining. In all of these areas, the pixel density is being continually increased as fabrication photolithography attains finer resolution and the device performance is improved. This leads to arrays with ever decreasing levels of stored energy per pixel and ever-increasing number of pixels per device. These trends lead to lower pixel output signals that are more susceptible to interconnect signal losses, cross-talk and external noise, all of which are made worse by the increase in the number of pixels and in the pixel density. One approach to overcoming these issues is to move the signal processing closer to the array, minimizing the number of interconnects and the interconnect length the raw pixel signal outputs must travel prior to pre-processing, such as amplification, noise suppression, and digitization. One innovative approach to achieving this is to use 3-D stacking of the preprocessing electronics for each pixel directly behind the sensor array. This paper will describe the development of a high density, 3-D stacking technology that is being applied to an 8000 pixel array sensor.

In this paper we give a brief report on the development of simple direct- and indirect-detection imagers for proton radiography experiments. We outline a conceptual design for a novel, multi-frame 5 mega frames per second (Mfs) hybrid imager. The high-density interconnect is identified as a critical enabling technology. We present a description of a 3D electronics packaging cube, which was completed in a recent feasibility study.

This paper describes the technical approach and progresses of the POINT program. This project is a collaborative effort among GE, Honeywell, AMP, AlliedSignal, Columbia University and University of California at San Diego, sponsored by DARPA/ETO to develop affordable optoelectronic packaging and interconnect technologies for board and backplane applications. In this paper, we report the development of a backplane interconnect structure using polymer waveguides to an interconnect length of 280 mm to demonstrate high density and high speed interconnect, and the related technical development efforts on: (a) a high density and high speed VCSEL array packaging technology that employs planar fabrication and batch processing for low-cost manufacturing, (b) passive alignment techniques for reducing recurrent cost in optoelectronic assembly, (c) low-cost optical polymers for board and backplane level interconnects, and (d) CAD tools for modeling multimode guided wave systems and assisting optoelectronic packaging mechanical design.

An innovative embedded chip MCM technology is being developed to address the packaging needs of the high volume, non‐military electronics industries. This development has evolved out of the GE High Density Interconnect (HDI) embedded chip MCM technology that was aimed at very high performance electronics in harsh military environments. In the HDI process, multiple bare chips are placed into cavities formed in a ceramic substrate and interconnected using an overlay polymer film, thin film metallisation and laser formed vias. Multiple levels of fine line (20 to 40 microns) interconnections and reference planes are used to form the circuit. In this new process, a plastic encapsulated substrate is formed by moulding a polymer resin around the bare die after placement on to a flat polymer film pre‐coated with an adhesive layer. After curing of the resin, the circuit is formed by patterning via holes through the polymer film to the components, metallising the polymer film and patterning the metal into the desired interconnect pattern. Feature sizes are readily scaled to the complexity needed by the circuit, permitting the use of lower cost and higher yield board photopatterning processes and equipment. This paper will cover the development of this low cost technology and will describe the process. It will also describe the thermal, mechanical and electrical features of this process and show actual working prototype modules.

Non-military/non-computer electronics industry segments such as PCs, workstations, portable electronics, automotive, medical, automated test equipment and high end consumer, are evolving to higher complexity and higher performance circuits and components. At the same time, many of these industry segments are being driven to shrink size, weigh and power dissipation. Standard low cost packaging approaches such as thru-hole PCB and chip and wire hybrids, can no longer efficiently interconnect these more complex circuits. These industry segments are being forced to turn to new higher performance packaging approaches such as SMT, MCM and COB. This paper describes the development of an innovative embedded chip MCM technology that eliminates high cost structures, materials and processes in current thin film MCM technologies. A plastic encapsulated multichip technology has been developed in which an epoxy encapsulant is molded around bare die to form the MCM substrate. This new MCM process readily scales-up to high volume production and is inherently high yielding, while maintaining all of the performance advantages of the GE developed overlay HDI process. This paper describes the thermal, mechanical and chemical stability issues that drove this development, the process used to fabricate the modules and the cost and yield advantages associated with this structure.< >