Semiconductor photonic emitters operating in the UV range remain an elusive goal. Attention has focused mainly on III‐Nitrides. However a large lattice constant difference between the III‐Nitride layers and compatible substrates results in high densities of misfit dislocations and consequently the device performance is adversely affected. An alternative novel material system, γ‐CuCl on silicon, is investigated. Properties of the exciton luminescence from vacuum deposited CuCl films on Si(100) and Si(111) are studied using temperature dependent photoluminescence (PL) spectroscopy. Four peaks attributed to the free exciton (Z3) (3.203 eV), bound exciton (I1) (3.181 eV), bi‐exciton (M) (3.159 eV) and bound bi‐exciton (N1) (3.134 eV) are identified from the PL spectrum at 10 K. A free exciton peak at 3.230 eV is observed at room temperature. The binding energies for the bound exciton, bi‐exciton and bound bi‐exciton are determined. Parameters, extracted from the temperature dependence of the Z3 PL peak intensity, energy and line‐width, have been compared with CuCl films on different substrates and in single crystal form. The luminescence properties of the CuCl on Si material system are found to compare well with reports for single crystal CuCl. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

γ-CuCl is a wide-band gap (Eg=3.395eV at 4K), direct band gap, semiconductor material with a cubic zincblende lattice structure. A very large exciton binding energy (190meV), assures efficient exciton-based emission at room temperature. Its lattice constant, aCuCl=0.541nm means that the lattice mismatch to Si (aSi=0.543nm) is <0.5%.γ-CuCl on Si—the growth of a wide-band gap, direct band gap, optoelectronics material on silicon substrate is a novel material system, with compatibility to current Si-based electronic/optoelectronics technologies. Both n-type and p-type CuCl will be required for development of homojunction light-emitting diodes (LEDs). The authors report on the impact of incorporation of Zn for n-type doping of CuCl by co-evaporation of CuCl and ZnCl2.Polycrystalline Zn-doped γ-CuCl thin films are grown on Si (111), Si (100), and glass substrates by physical vapour deposition. X-ray diffraction (XRD) studies confirm that this n-doped CuCl has a cubic zincblende structure with a preferred (111) orientation. Several excitonic bands are evident in low-temperature photoluminescence (PL) measurements such as the Z3 free exciton at ∼388nm; I1-bound exciton at ∼392nm and M free biexciton at ∼393nm. Cathodoluminescence (CL) and PL reveal a strong room temperature Z3 excitonic emission at ∼385nm. Electrical measurements indicate n-type conductivity with resistivity ∼34Ωcm.

We have probed the luminescence properties of a wide-band-gap, direct band-gap optoelectronic material, grown on closely lattice-matched silicon substrates, namely, γ-CuCl on Si. This material system is compatible with current Si or GaAs-based electronic/optoelectronic technologies. Polycrystalline epitaxy of CuCl can be controlled such that it maintains an orientation similar to the underlying Si substrate. Importantly, chemical interactions between CuCl and Si are eliminated. Photoluminescence and cathodoluminescence results for CuCl, deposited on either Si (100) or Si (111), reveal a strong room-temperature Z3 excitonic emission at ∼387nm. We have developed and demonstrated the room-temperature operation of an ultraviolet electroluminescent device fabricated by the growth of γ-CuCl on Si. The application of an electrical potential difference across the device results in an electric field, which promotes light emission through hot-electron impact excitation of electron-hole pairs in the γ-CuCl. Since the excitonic binding energy in this direct band-gap material is of the order of 190meV at room temperature, the electron-hole recombination and subsequent light emission at ∼380 and ∼387nm are mediated by excitonic effects.

Copper (I) Chloride is a wide band gap semiconductor with great potential for silicon-based optoelectronics due to the fact that is closely lattice matched with silicon. This work examines the deposition of CuCl thin films by magnetron sputtering on silicon and glass substrates. Film structural and morphological properties are studied with X-ray diffraction and atomic force microscopy. Optical absorbance and luminescence spectra of CuCl thin films are analysed in order to study the excitonic features. The influence of deposition process parameters and post annealing on the film properties are also reported.

γ-CuCl is a wide-bandgap (Eg = 3.395eV), direct bandgap, semiconductor material with a cubic zincblende lattice structure. Its lattice constant, aCuCl = 0.541 nm, means that the lattice mismatch to Si (aSi = 0.543 nm) is <0.5%. γ-CuCl on Si-the growth of a wide-bandgap, direct bandgap, optoelectronics material on silicon substrates is a novel material system, with compatibility to current Si based electronic/optoelectronics technologies. The authors report on early investigations consisting of the growth of polycrystalline, CuCl thin films on Si (100), Si (111), and quartz substrates by physical vapour deposition. X-ray diffraction (XRD) studies indicate that CuCl grows preferentially in the <111> direction. Photoluminescence (PL) and Cathodoluminescence (CL) reveal a strong room temperature Z3 excitonic emission at ~387nm. A demonstration electroluminescent device (ELD) structure based on the deposition of CuCl on Si was developed. Preliminary electroluminescence measurements confirm UV light emission at wavelengths of ~380nm and ~387nm, due to excitonic behaviour. A further emission occurs in the bandgap region at ~360nm.

γ-CuCl is a wide-bandgap (E g = 3.395 eV), direct bandgap, semiconductor material with a cubic zincblende lattice structure. Its lattice constant, aCuCl = 0.541 nm, means that the lattice mismatch to Si (aSi = 0.543 nm) is < 0.5%. γ-CuCl on Si—the growth of a wide-bandgap, direct bandgap, optoelectronics material on silicon substrates is a novel material system, with compatibility to current Si based electronic/optoelectronics technologies.

The control and characterisation of wafer defect and strain distributions is of crucial importance for the development of advanced Ultra Large Scale Integration (ULSI) circuits. Within the IC manufacturing sector 0.35 μm linewidth-based advanced Complementary Metal Oxide Semiconductor (CMOS) logic has recently emerged at a high level of maturity, to be closely followed by an even more demanding 0.25 μm process. One very important issue is the need to ensure a uniform, high quality Si substrate, i.e. minimise defect densities and eliminate strain distributions in the starting wafer material. Synchrotron section and back-reflection topographic techniques were applied to 200 mm diameter p-Si wafers, upon which, boron and arsenic doped epitaxial silicon layers had been deposited. These wafers were supplied from manufacturers around the globe and revealed substantial differences in the overall quality of the epilayers and substrates. In all wafers the substrate quality varied significantly with position across the wafer, as measured by the presence of oxygen-related defects and dopant strain homogeneity. The strain field uniformity, induced by the growth of lightly doped Si epilayers, was also observed to vary qualitatively with location on a wafer. Back-reflection topographs verify that the quality of the epilayer-substrate interface improved as the thickness of the epilayer, or the gradient of dopant density across the interface, is reduced. Cellular strain-related structures, of the order of a few hundred μm in circumference, have been observed in the more stressed p on p+ samples. Topographic results are in agreement with those obtained from X-ray diffraction measurements. Finally, an examination was carried out into the quality of commercially supplied 200 mm diameter Si wafers, revealing differences in the overall quality of the wafers.

Local oxidation of silicon (LOCOS) isolation technology is becoming increasingly unusable for critical dimensions of 0.25 μm and below, due to the intolerably large dimension of the oxide “bird'sbeak”. Therefore, this technique has been replaced by a process called shallow trench isolation (STI) which uses deposited dielectrics to fill trenches etched in the silicon between the active areas. One of the chief drawbacks to STI is the tendency of such structures to be highly stressed, especially after the oxide/dielectric backfill, which can have a deleterious impact on the electrical performance of fabricated devices. It is essential to monitor the stress/strain fields generated by shallow trench isolation structures. Synchrotron X-ray topography (SXRT), a genuinely non-destructive technique, has been employed to provide in situ stress evaluation during the development of an STI-based complimentary metal oxide semiconductor (CMOS) integrated circuit process. Various process options were evaluated and the data was compared with electrical n+/p diode leakage and micro-Raman spectroscopy data.

The continued decrease in critical dimensions and increasing integration levels in Si CMOS technology is imposing ever tighter constraints on quality control parameters for the IC manufacturing industry. One very important issue is the need to ensure a uniform, high quality Si substrate, i.e. minimise defect/dislocation densities and eliminate strain distributions in the starting wafer material. A comprehensive Synchrotron X-Ray Topography (SXRT) study was applied to commercially supplied 200mm diameter Si wafers. These wafers, which all included a surface Si epilayer growth were supplied from manufacturers from around the globe. The study revealed not only differences in the overall quality of the wafers, but also differences in the quality of the individual Silicon epilayers and substrates. In all wafers the substrate quality varied dramatically with position across the wafer, as measured by the distribution of oxygen precipitates and stacking faults in the wafer. This distribution also varied significantly from manufacturer to manufacturer. The strain fields induced by the growth of lightly doped Si epilayers were also observed to qualitatively vary with location on a wafer, together with (as expected) thickness of the epilayers. The results clearly indicate that optimal quality control for such commercial wafers has not yet been achieved.