Network-on-chip (NoC) communication architectures are emerging as the most scalable and efficient solution to handle on-chip communication challenges in the multicore era. In NoCs, power estimations in the early stages of the design help the designers to optimize the design for energy consumption and efficiently map applications to achieve low-power solutions. However, in 90-nm designs or below, the impact of parasitics not only influence timing closure, but also leads to variability in power and area budgets among different NoC architectures. There is a growing need for advanced design methodologies to overcome these issues in NoC designs. This paper presents a system-level design methodology based on layout and power models to achieve low-power and high-performance NoC designs. The impact of global interconnects with and without repeater insertion on the bandwidth and power is considered. Width and spacing of global interconnects and its effect on performance and power dissipation are analyzed. For architectural-level power analysis, different router designs for Chip-Level Integration of Communicating Heterogeneous Elements (CLICHE), Butterfly Fat Tree (BFT), Scalable, Programmable, Integrated Network (SPIN), and Octagon NoC architectures are implemented using ARMs 65-nm standard cell library in 65-nm Taiwan Semiconductor Manufacturing Corporation (TSMC) process. The router designs are synthesized in RVT process using a ${V}_{\rm dd}$ of 1.0 V and a temperature of 25$^{\circ}{\rm C}$ . Synopsys Prime Time-PX design tool is used for calculating average power dissipation of the router designs.

An asynchronous architecture is proposed to achieve a low-power network-on-chip (NoC). The area of the asynchronous switch is increased by 25% as compared to the synchronous switch. However, the power dissipation of the asynchronous architecture could be decreased by up to 55%. Even though clock gating is used, the asynchronous design achieves significant power reduction of 28%. The total metal resource required to implement the asynchronous design is decreased by up to 12%. As technology advances and network density increases, the reduction in power dissipation reaches 22% for 256 IPs with the same chip size. The asynchronous butterfly fat tree (BFT) architecture dissipates the minimum power as compared to other NoC topologies. (c) 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Network-on-Chip (NoC) architectures have been shown to solve on chip communication issues in larger SoC designs, but its success heavily depends on the total power budget they may require. Designing power efficient NoCs or finding ways to reduce NoC power is thus extremely important. In this paper, power efficiency of Synchronous and Asynchronous Octagon NoC architectures is presented. The relation between ccdata (the activity factor of the data transfers between the two switches) and power efficiency of the two networks is analyzed. Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfers between two switches (celata) satisfies a particular range. The area of Asynchronous switch is increased by 25% as compared to Synchronous switch. However the power dissipation of the Asynchronous architecture is decreased by 27% in comparison to the power dissipation of the Synchronous architecture when adata equals 0.2 and the activity factor of the control signals is 1/64 of the adata. The total metal resources required to implement Asynchronous design are decreased by 4 %.

Network-on-Chip (NoC) communication architectures have been recognized as the most scalable and efficient solution for on chip communication challenges in the multi-core era. Diverse demanding applications coupled with the ability to integrate billions of transistors on a single chip are some of the main driving forces behind ever increasing performance requirements towards the level that requires several tens to over a hundred of cores per chip, with aggregate performance exceeding one trillion operations per second. Such tera-scale many-core processors will be highly integrated System-on-Chip designs (SoC) containing a variety of on-chip storage elements, memory controllers, and input/output (I/O) functional blocks. Small scale multicore processors so far have been a great commercial success and found applicability in high bandwidth, computer intensive applications including high performance, throughput oriented, scientific computing, high performance graphics and 3-D immersive visual interfaces, as well as in decision and support systems. Systems using multi-core processors are now the norm rather than the exception. As the number of cores or components integrated into a single system is keep increasing, the design of on-chip communication architecture is becoming more challenging. The increasing number of components in a system translates into more

As IC geometries continue to shrink into the deep nanometer regime, interconnects can have a large impact on overall system performance, power consumption, cost and reliability. In 90 nm or lower technologies, wiring capacitance dominates gate capacitance, thus rapidly leading to increased interconnect-induced delay. Moreover, coupling capacitance becomes significant between adjacent wires due to tighter geometries and can no longer be ignored as a second order effect. As a consequence, traditional top-down approach taken in design methodology for a NoC based complex SoC designs is no longer effective. This paper address the impact of nanometer layout on the design of NoC, and shows the necessity to consider interconnect parasitic effects in early stages of design even when no physical layout is available. Global interconnects with and without repeater insertion are considered. The effects of the width and spacing of global interconnects on NoC performance such as delay, bandwidth, total repeater area and power dissipation is analyzed.

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at the Ohio State University, Columbus, has partnered with Texas Instruments to establish an IC test-engineering-oriented course. The course objectives are to familiarize students with industrial testing techniques and to help students obtain the fundamental skill sets required to be competent mixed-signal IC test engineers. A novel laboratory pedagogy is developed to achieve these objectives. The results of the classroom assignments and the feedback provided by students, faculty, and industry representatives indicate that the approach has successfully achieved these goals.

This paper describes a new course on mixed-signal IC test engineering, jointly established by the Department of Electrical and Computer Engineering (ECE) of The Ohio State University and Texas Instruments. The course is motivated by the lack of qualified test engineers in industry and the absence of this education at the collegiate level. The course objective is to help student obtain the fundamental skills required for a mixed-signal IC test engineer. The course structure and laboratory developments are covered in details. Students feedbacks based on anonymous survey indicate that the goals are well met.

Software Defined Radio (SDR) has gained much interest in recent years due to the advancements in FPGA technology. FPGA provides the capability of programming Analog Components (Mixers, PLL, Filters etc...) which were traditionally implemented in hardware. In this paper digital functional blocks that need to be programmed in FPGA core are designed and simulated using Matlab for Amplitude demodulation for Double Side Band (DSB) with carrier, Double Side Band with Suppressed Carrier (DSB-SC) and Single Side Band with Suppressed Carrier (SSB-SC). Sampling frequency of 4MHz is selected to ensure that sampling rate is greater than twice of maximum commercially available AM carrier frequency (of 1720 kHz) and carrier frequency of 610 kHz is used for simulations. This simulation result concludes the proper operation of the design.