Due to their potential to accomplish complicated missions more effectively, UAV swarms have attracted a lot of attention lately. UAV swarm offers enhanced intelligence, improved coordination, increased flexibility, survivability, and reconfigurability. It is a multi-disciplinary system that necessitates a tight integration of several sub-systems, including optimal trajectory planning, localization, task coordination, etc. This review covers the important aspects of UAV swarms including swarm formation control, communication, swarm path planning, autonomy, coordination, and security. It additionally explores recent technical advancements in UAV swarm algorithms that have made the development of complex UAV swarm systems possible. This paper also provides insight into ethical aspects and the use cases of UAV swarms in various military, civilian, and entertainment applications. This paper is concluded by highlighting the potential future directions and challenges of UAV swarm technology and the need for more research and development to exploit their potential fully. Overall, this paper presents a comprehensive review of UAV swarm technology, addressing its potential for revolutionizing many fields and supporting advancements in the future.

Motorbikes are an integral part of transportation in emerging countries, but unfortunately, motorbike users are also one the most vulnerable road users (VRUs) and are engaged in a large number of yearly accidents. So, motorbike detection is very important for proper traffic surveillance, road safety, and security. Most of the work related to bike detection has been carried out to improve accuracy. If this task is not performed in real-time then it loses practical significance, but little to none has been reported for its real-time implementation. In this work, we have looked at multiple real-time deployable cost-efficient solutions for motorbike detection using various state-of-the-art embedded edge devices. This paper discusses an investigation of a proposed methodology on five different embedded devices that include Jetson Nano, Jetson TX2, Jetson Xavier, Intel Compute Stick, and Coral Dev Board. Running the highly compute-intensive object detection model on edge devices (in real-time) is made possible by optimization. As a result, we have achieved inference rates on different devices that are twice as high as GPUs, with only a marginal drop in accuracy. Secondly, the baseline accuracy of motorbike detection has been improved by developing a custom network based on YoloV5 by introducing sparsity and depth reduction. Dataset augmentation has been applied at both image and object levels to enhance robustness of detection. We have achieved 99% accuracy as compared to the previously reported 97% accuracy, with better FPS. Additionally, we have provided a performance comparison of motorbike detection on the different embedded edge devices, for practical implementation.

Unmanned aerial vehicles (UAVs) equipped with onboard embedded platforms and camera sensors provide access to difficult-to-reach areas and facilitate in remote sensing and autonomous decision-making capabilities in disaster recovery and management applications. Onboard computations are preferred due to connectivity, privacy, and latency problems. However, edge implementation becomes challenging because of limited onboard hardware resources (in terms of area, power, and storage). In this article, we propose a UAV assisted edge computation framework that compresses the convolutional neural network (CNN) models to be run on an onboard embedded graphics processing unit (GPU) for real-time disaster scenario classification. We use an imbalanced dataset named, Aerial Image Database for Emergency Response (AIDER), to replicate real-world disaster scenarios. Our experimental results show that optimized compressed model’s throughput is increased by about 99% which is up to $92\times $ faster than the native model. Furthermore, the model size reduction enabled through the proposed framework is about 84% without compromising accuracy and thus makes it suitable for edge GPUs.

Object detection is a critical task that becomes difficult when dealing with onboard detection using aerial images and computer vision technique. The main challenges with aerial images are small target sizes, low resolution, occlusion, attitude, and scale variations, which affect the performance of many object detectors. The accuracy of the detection and the efficiency of the inference are always trade-offs. We modified the architecture of CenterNet and used different CNN-based backbones of ResNet18, ResNet34, ResNet50, ResNet101, ResNet152, Res2Net50, Res2Net101, DLA-34, and hourglass14. A comparison of the modified CenterNet with nine CNN-based backbones is conducted and validated using three challenging datasets, i.e., VisDrone, Stanford Drone dataset (SSD), and AU-AIR. We also implemented well-known off-the-shelf object detectors, i.e., YoloV1 to YoloV7, SSD-MobileNet-V2, and Faster RCNN. The proposed approach and state-of-the-art object detectors are optimized and then implemented on cross-edge platforms, i.e., NVIDIA Jetson Xavier, NVIDIA Jetson Nano, and Neuro Compute Stick 2 (NCS2). A detailed comparison of performance between edge platforms is provided. Our modified CenterNet combination with hourglass as a backbone achieved 91.62%, 75.61%, and 34.82% mAP using the validation sets of AU-AIR, SSD, and VisDrone datasets, respectively. An FPS of 40.02 was achieved using the ResNet18 backbone. We also compared our approach with the latest cutting-edge research and found promising results for both discrete GPU and edge platforms.

Coherent pulse integration is a well-known technique for effective target detection with increased output signal-to-noise ratio (SNR). Radon Fourier transform (RFT) uses a long-time coherent integration technique for improved target detection in a 3-D search but increases the parameters search time. This article presents a new approach of segmented RFT (SRFT) for fast detection of high-speed targets without significantly degrading the detection performance.SRFT divides the received echo data matrix into an arbitrary number of segments along the slow-time dimension of the data matrix. Each segment is a complete independent data matrix, which can proceed independently and in parallel fashion. This article implements a complete pipeline of radar receiver with SRFT to validate its integration in a radar signal processor. Experiments show that the parameters search time of SRFT is reduced by N-k times when compared with RFT, where N(k )is the number of segments. There is a negligible degradation of 0.035 dB in SNR when compared with standard RFT for 120 pulses. The difference is further reduced, as the number of pulses is increased.

Network-on-Chip (NoC) has been unfolded as a superior alternative for integrating a considerably greater extent of cores on a single chip. Recently, multi-core systems have become prevalent because of the increased processing demands for high-performance embedded applications. Application mapping techniques play a significant role in enhancing the extensive performance of such complex multi-core platforms. Developing and implementing efficient application mapping techniques are required for system design to meet the demand of such complicated multi-core systems. The paper primarily focuses on dynamic application mapping techniques, classifying them into a number of subcategories. It highlights such approaches and techniques that aim to enhance the performance of the NoC-based systems by optimizing them in terms of communication cost, latency, energy consumption, power, execution, and computational time. Future challenges, trends, and simulation tools have also been spotlighted.

In this paper, keystone transform with a P-chip interpolator is used to improve ambiguity resolution and for compensating linear range migration. These non-idealities are caused by high radial velocities in ultra-wideband synthetic aperture radar applications. For increased efficiency, P-chip interpolator is used to re-sample the slow time data of the radar data matrix. The adopted sequence involves generation of signal model followed by Keystone transform with the proposed interpolation technique. Some numerical results from simulations have been presented with reference to a wide-band signal in a radar dataset.

Due to the excessive use of cloud-based machine learning (ML) services, the smart cyber-physical systems (CPS) are increasingly becoming vulnerable to black-box attacks on their ML modules. Traditionally, the black-box attacks are either transfer attacks requiring model stealing, or score/decision-based gradient estimation attacks requiring a large number of queries. In practical scenarios, especially for cloud-based ML services and timing-constrained CPS use-cases, every query incurs a huge cost, thereby rendering state-of-the-art decision-based attacks ineffective in such settings. Towards this, we propose a novel methodology for automatically generating an extremely fast and imperceptible decision-based attack called FaDec. It follows two main steps: (1) fast estimation of the classification boundary by combining the half-interval search-based algorithm with gradient sign estimation to reduce the number of queries; and (2) adversarial noise optimization to ensure the imperceptibility. For illustration, we evaluate FaDec on the image recognition and traffic sign detection using multiple state-of-the-art DNNs trained on CIFAR-10 and the German Traffic Sign Recognition Benchmarks (GTSRB) datasets. The experimental analysis shows that the proposed FaDec attack is 16x faster compared to the state-of-the-art decision-based attacks, and generates an attack image with better imperceptibility for a much lesser number of iterations, thereby making our attack more powerful in practical scenarios. We open-sourced the complete code and results of our methodology at https://github.com/fklodhi/FaDec.

Training data is crucial in ensuring robust neural inference, and deep neural networks (DNNs) are heavily dependent on this assumption. However, DNNs can be exploited by adversaries that facilitate various attacks. Adversarial defenses include several techniques, some of which happen during the preprocessing stages (i.e., noise filtering, etc.). This article analyzes the impact of some preprocessing filters, and proposes a selective preprocessing method which increases robustness and reduces the computational complexity.-Theocharis Theocharides, University of Cyprus

Adversarial examples have emerged as a significant threat to machine learning algorithms, especially to the convolutional neural networks (CNNs). In this paper, we propose two quantization-based defense mechanisms, Constant Quantization (CQ) and Trainable Quantization (TQ), to increase the robustness of CNNs against adversarial examples. CQ quantizes input pixel intensities based on a “fixed” number of quantization levels, while in TQ, the quantization levels are “iteratively learned during the training phase”, thereby providing a stronger defense mechanism. We apply the proposed techniques on undefended CNNs against different state-of-the-art adversarial attacks from the open-source Cleverhans library. The experimental results demonstrate 50%-96% and 10%-50% increase in the classification accuracy of the perturbed images generated from the MNIST and the CIFAR-10 datasets, respectively, on commonly used CNN (Conv2D(64, 8×8)-Conv2D(128, 6×6)-Conv2D(128, 5×5) - Dense(10) - Softmax()) available in Cleverhans library.

Due to data dependency and model leakage properties, Deep Neural Networks (DNNs) exhibit several security vulnerabilities. Several security attacks exploited them but most of them require the output probability vector. These attacks can be mitigated by concealing the output probability vector. To address this limitation, decision-based attacks have been proposed which can estimate the model but they require several thousand queries to generate a single untargeted attack image. However, in real-time attacks, resources and attack time are very crucial parameters. Therefore, in resource-constrained systems, e.g., autonomous vehicles where an untargeted attack can have a catastrophic effect, these attacks may not work efficiently. To address this limitation, we propose a resource efficient decision-based methodology which generates the imperceptible attack, i.e., the RED-Attack, for a given black-box model. The proposed methodology follows two main steps to generate the imperceptible attack, i.e., classification boundary estimation and adversarial noise optimization. Firstly, we propose a half-interval search-based algorithm for estimating a sample on the classification boundary using a target image and a randomly selected image from another class. Secondly, we propose an optimization algorithm which first, introduces a small perturbation in some randomly selected pixels of the estimated sample. Then to ensure imperceptibility, it optimizes the distance between the perturbed and target samples. For illustration, we evaluate it for CFAR-10 and German Traffic Sign Recognition (GTSR) using state-of-the-art networks.

Generative Adversarial Networks (GANs) have gained importance because of their tremendous unsupervised learning capability and enormous applications in data generation, for example, text to image synthesis, synthetic medical data generation, video generation, and artwork generation. Hardware acceleration for GANs become challenging due to the intrinsic complex computational phases, which require efficient data management during the training and inference. In this work, we propose a distributed on-chip memory architecture, which aims at efficiently handling the data for complex computations involved in GANs, such as strided convolution or transposed convolution. We also propose a controller that improves the computational efficiency by pre-arranging the data from either the off-chip memory or the computational units before storing it in the on-chip memory. Our architectural enhancement supports to achieve 3.65x performance improvement in state-of-the-art, and reduces the number of read accesses and write accesses by 85% and 75%, respectively.

Most of the data manipulation attacks on deep neural networks (DNNs) during the training stage introduce a perceptible noise that can be catered by preprocessing during inference, or can be identified during the validation phase.Therefore, data poisoning attacks during inference (e.g., adversarial attacks) are becoming more popular.However, many of them do not consider the imperceptibility factor in their optimization algorithms, and can be detected by correlation and structural similarity analysis, or noticeable (e.g., by humans) in multi-level security system.Moreover, majority of the inference attack rely on some knowledge about the training dataset.In this paper, we propose a novel methodology which automatically generates imperceptible attack images by using the back-propagation algorithm on pre-trained DNNs, without requiring any information about the training dataset (i.e., completely training dataunaware).We present a case study on traffic sign detection using the VGGNet trained on the German Traffic Sign Recognition Benchmarks dataset in an autonomous driving use case.Our results demonstrate that the generated attack images successfully perform misclassification while remaining imperceptible in both "subjective" and "objective" quality tests.

Recent studies have shown that slight perturbations in the input data can significantly affect the robustness of Deep Neural Networks (DNNs), leading to misclassification and confidence reduction. In this paper, we introduce a novel technique based on the Selective Sobel Convolution (SSC) operation in the training loop, that increases the robustness of a given DNN by allowing it to learn important edges in the input in a controlled fashion. This is achieved by introducing a trainable parameter, which acts as a threshold for eliminating the weaker edges. We validate our technique against the attacks of Cleverhans library on Convolutional DNNs against adversarial attacks. Our experimental results on the MNIST and CIFAR10 datasets illustrate that this controlled learning considerably increases the accuracy of the DNNs by 1.53% even when subjected to adversarial attacks.

Dynamic power-gating has been shown to reduce FPGA static leakage power significantly. In this paper, we propose a high-level synthesis (HLS) compiler-assisted framework that automatically detects the hierarchical power-gating opportunities, and turns off accelerators when they are not required. Unlike previous work which considers turning off entire accelerators when they are not required, our technique is more fine-grained, in that it allows turning off a portion of an accelerator when other parts of an accelerator are running. Results on CHStone benchmarks show that hierarchical power-gating can save up to 31

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current tool-chains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable power-gating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.

The dynamic partial reconfiguration of FPGAs is a method which modifies parts of FPGA configuration memory at run-time. The hardware resources and time overhead needed to perform a partial reconfiguration (PR) can significantly impact overall system cost and performance and must be considered early in the design cycle. Unfortunately, predicting reconfiguration overhead is difficult especially in the presence of non-deterministic factors such as the sharing of resources with traffic not related to the PR process. Thus, current design practices include the measurement of overhead but only after the system has been built thus limiting the number of candidates that can be evaluated. We propose a flexible approach for modeling the PR datapath based on Queueing Theory such that we can estimate performance trends and bottlenecks of the PR process while considering the impact of shared resources. Performance trends are provided for an example system to demonstrate the effectiveness of the approach.