Presents the recipients of IEEE Microwave Theory and Technology Society awards for 2026.

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This paper presents a high-performance millimeter-wave voltage-controlled oscillator (VCO). The circuit utilizes an impedance-boosted Colpitts topology to achieve a superior tradeoff between power consumption, phase noise, and tuning range. The VCO demonstrates a continuous tuning range of 12.7%, spanning from 33.8 GHz to 38.4 GHz. At a fundamental frequency of 35.2 GHz, a minimum phase noise of −107.1 dBc/Hz is achieved at a 1MHz offset. With a core power consumption of 36.8mW and an active area of 0.095mm2, the design attains a peak Figure of Merit (FoM) of 182.4 dBc/Hz, a FoMT of 184.4 dBc/Hz and a FoMA of 192.6 dBc/Hz. The circuit was fabricated in a 90nm SiGe BiCMOS process with ft/fmax of 300 GHz/500 GHz, respectively.

A self-biased Class-$\mathrm{F}_{3}$ topology demonstrating a good phase noise performance is proposed in this paper. It exhibits a phase noise of $96 \text{dBc} / \text{Hz}$ at 1 MHz offset from the carrier at 24.0 GHz over $22.5-25.8 \text{GHz}$ tuning range with a figure-of-merit of $1 7 3. 0\ \text{d B c} / \text{H z}$. With an exceptionally compact core area of only $0.013\ \text{mm}^{2}$, the proposed voltage-controlled oscillator (VCO) demonstrates excellent suitability for high-speed data link applications implemented in advanced technology nodes, thereby enabling cost-efficient integration. The oscillator is manufactured on GlobalFoundries 12LP+ FinFET CMOS technology and draws only 8.28 mA from a 1.4 V supply.

This paper presents a local oscillator signal generation scheme at D-band frequencies for homodyne transmitters and transceivers that require quadrature phases and reduced susceptibility to oscillator pulling by the integrated power amplifiers. A voltage-controlled oscillator at two-thirds of the output frequency is used to drive a static frequency divider that generates quadrature phases. Based on the divider outputs, subsequent mixing stages generate quadrature D-band signals. Individual characterization of the W-band oscillator core shows a tuning range from 86.7 to 94.3 GHz while the divider-based quadrature generator’s input frequency range covers the complete W-band and achieves < 2° divider output phase error at most frequencies. The oscillator-enabled quadrature generator operates over a 11.2 GHz (8.2 %) tuning range from 129.9 to 141.1 GHz, achieving a phase noise of -78 dBc/Hz at 1 MHz offset and a quadrature phase error of 6.5°. The circuits are fabricated using 130 nm BiCMOS technology.

This paper presents a 5-stage wideband variable gain amplifier (VGA) integrated in 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit comprises three different core circuit topologies composed of an input buffer, three gain control stages, and a high-power output stage. The VGA achieves a 30 dB gain with a power consumption of 44mW, exhibiting a continuous tuning range of 33 dB, covering a 3 dB bandwidth of 21 GHz while occupying an area of 0.077mm(2). The VGA is optimized for operation within high-data rate 6G receiver systems.

Current surface acoustic wave based duplexers have the drawback of fixed frequency response, leading to complex RF front ends with a high amount of duplexers and switches. New approaches for tunable duplexers such as electrical balance duplexers (EBD) have the drawback of limited insertion loss or the need of active components which introduce noise. In this work we present a variation of the electrical balance duplexer overcoming this fundamental 3 dB insertion loss limitation for frequency division duplex (FDD) applications. The measurements showed an insertion loss smaller 3 dB for a varactor based realization.

This paper presents a D-Band IQ mixer design based on two double-balanced Gilbert cell mixers with a differential common collector output stage to buffer the load. The quadrature phases are generated in the LO feed of the mixer using a single ended Lange coupler to create a 90 degrees phase difference, followed by Marchand baluns that produce differential signals. It was designed as a low noise amplifier (LNA) first, mixer second receiver architecture used in a D-Band communication system utilizing QPSK or higher order modulation schemes. It ' s fabricated as a standalone component for characterization in a 130nm SiGe BiCMOS technology with f(t) / f(max) of 250GHz / 370 GHz. With a total power consumption of 75mW from a 3.5V supply the design offers a measured conversion gain of 2.5 dB at an IF frequency of 500MHz and an input 1 dB compression point (IP1dB) of -10dBm all while being integraded in an area of 0.56mm(2).

This work proposes a D-band 5th sub-harmonic injection-locked oscillator (SILO) implemented in a 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit utilizes a serial injection technique, including p-MOS diodes, to enhance the non-linear transconductance and increase the generation of sub-harmonic currents and, thus, enlarging the lock range. Compact self-biased inverter input buffers are employed to provide signal amplification and steep harmonic-rich square voltage waveforms. The SILO achieves a 4 GHz lock range at nominal bias, extendable by back-gate biasing to an overall lock range of 6.8 GHz from 145.6 to 152.4 GHz. The output power reaches -5.7dBm while consuming only 31mW and occupying a compact core area of 200 x 95 mu m(2).

This paper presents an 8-port 10 MHz – 110 GHz vector network analysis measurement setup, achieving high magnitude accuracy by using two separate commercially available network analyzers with frequency extenders. Compared to a single VNA setup, the approach achieves a maximum absolute linear magnitude error of less than 0.05 up to 90 GHz. The paper describes the necessary hardware interconnects, along with the proposed software algorithm. The attained accuracy and dynamic range are demonstrated to be suitable for the 8-port characterization of crosstalk in densely packed signal routing environments, such as terabit-per-second chip-to-chip interfaces, extending to a higher frequency range than what is currently commercially available.

Joint Communication and Sensing (JCAS) is a key enabler for future 6G networks, allowing data transmission and environmental sensing through shared spectral and hardware resources. To address challenges such as the sensing-communication trade-off, hardware limitations, and multi-user interference, we propose a scalable Multiple Input Multiple Output (MIMO) framework based on Uniform Rectangular Arrays (URA) with partially connected hybrid beamforming (PC-HBF). On the transmitter side, a fairnessaware beamforming optimization maximizes sensing gain while ensuring communication quality, solved via an Interior-Point Method (IPM) with adaptive initialization for improved convergence. At the receiver, a two-stage Block Orthogonal Matching Pursuit (Block-OMP) with Adaptive Dictionary Selection and Refinement (ADSR) enhances combining accuracy under hardware constraints while maintaining low complexity. For radar sensing, we introduce a hybrid direction-of-arrival (DoA) estimation method combining Beamscan and MUSIC algorithms. This design enables accurate angle estimation despite PC-HBF limitations, providing a practical sensing solution for JCAS scenarios. Simulation results demonstrate the practical effectiveness of our design: IPM-based beamforming converges within 15 iterations, ADSR-enhanced combining improves spectral efficiency by up to 1 dB over baseline OMP, approaching the performance of fully digital beamforming while supporting joint sensing, and the DoA method resolves targets spaced as closely as 5°. These gains underline the framework’s potential in real-world applications such as smart mobility and autonomous driving, enabling scalable and high-performance JCAS systems.

This paper presents a novel implementation of a substrate-based broadband integrated loop antenna that works without any lumped components. A compact substrate-integrated Moebius antenna was built from an integrated coaxial wave guide using an edge plating technique. The antenna was integrated with a wire-wound balun to provide a single-ended system and galvanic isolation between the EMP measurement chamber and measurement equipment.

This paper presents a 5-stage wideband variable gain amplifier (VGA) integrated in 22nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit comprises three different core circuit topologies composed of an input buffer, three gain control stages, and a high-power output stage. The VGA achieves a 30dB gain with a power consumption of 44mW, exhibiting a continuous tuning range of 33dB, covering a 3dB bandwidth of 21GHz while occupying an area of 0.077mm2. The VGA is optimized for operation within high-data rate 6G receiver systems.

As 6G and beyond communication systems are not only expected to further increase data-transfer rates and latency, but also enable integration of sensing-based features in the private, industrial and public domain, sub-THz frequencies receive increasing attention due to unprecedented bandwidths and precise sensing capabilities. Making use of these advantages requires advanced array-based transceivers to achieve high angular resolution and overcome the inherent limitations of reduced antenna area and semiconductor technology. This paper gives an overview of numerous hardware challenges and solutions related to high-frequency performance and implementation difficulties that arise from application requirements, their impact on architectural approaches and component level performance.

This paper presents an area-efficient, three-stage, differential variable gain amplifier (VGA) integrated into a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. Variable gain is realized by tuning the common source stage's transconductance, varying the current through a parallel diode-connected load. The VGA features a linear dB gain behavior across a wide tuning range of over 20 dB. The amplifier stages are DC-coupled to avoid the gain reduction at the low baseband frequencies. In the output stage, inductive peaking is used to enlarge the bandwidth, allowing the VGA to cover a 3 dB bandwidth of 17 GHz. One primary design goal is efficient area usage, which is achieved by minimizing the number of required inductors, resulting in a core area of $0.035 \text{mm}^{2}$. The VGA attains a maximal gain of 23 dB, a linear dB tuning range from −3 to 18 dB, and a maximum output power $\mathrm{P}_{\text{sat }}$ of 8.9 dBm, a maximum PAE of 6.4% while showing a comprehensive noise figure of 5 to 11 dB. Supplied by 1.4 V, the circuit's power consumption is 112 mW.

This paper presents a non-primitive pseudo-random binary sequence (PRBS) generator for sensing application, implemented using ten true single-phase clock (TSPC) flip-flops (FF) configured as a linear feedback shift register (LFSR). The feedback is applied after the tenth and ninth FF using an exclusive OR (XOR) operation, resulting in a shortened sequence length of 889. The PRBS circuit is implemented in a 12nm FinFET bulk technology, occupying a core area of 22 mu m(2). It operates at a maximum data rate of 20 GBit/s with a supply voltage of 0.8V. The total power consumption of the breakout circuit, including support circuitry is 3.52mW. Whilst the the LFSR core power consumption is 0.72mW. The PRBS achieves a figure of merit (FoM) of 3.67 fJ/bit based on the maximum data rate and power consumption.

This paper presents a fully integrated push-push voltage-controlled oscillator (VCO) using a modified Meissner (Armstrong) topology based on a single asymmetric transformer and varactor, which achieves a frequency tuning range (FTR) of $11.6 \%$ between 148.4 GHz and 166.7 GHz at a maximum output power of -1.7dBm. The target application is the generation of flexible local oscillator (LO) signals for Joint Communication and Sensing (JCAS) applications in the D-band. A minimum phase noise of -80.6 dBc/Hz at 1 MHz offset is achieved at a power consumption of 54 mW from a 1.8 V supply, which corresponds to a $\mathrm{FOM}_{\mathrm{T}}$ of $-168.5 \mathrm{dBc} / \mathrm{Hz}$. The VCO test structure is fabricated using a $130 \mathrm{~nm} \operatorname{SiGe} \mathrm{BiCMOS}$ technology with $f_{\mathrm{t}} / f_{\text {max }}$ of $250 \mathrm{GHz} / 370 \mathrm{GHz}$ and is co-integrated with a static divide-by-32 frequency divider chain that provides an output at around 2.5 GHz for interfacing with an external phase-locked loop (PLL).

A novel power sensing method, integrated in low noise amplifier architectures is presented and demonstrated in 130 nm SiGe BiCMOS technology. The power sensor architecture can be utilized to detect blocking signals by supply current variations caused from different amplifier saturation states. Therefore the combined amplifier/power sensor architecture overcomes the need of additional components in the RF signal path for input power sensing. Two sensor architectures are compared while one is implemented. The architectures ability to indicate input power by amplifier saturation is proven by measurement. It is shown that the sensor gives direct feedback at early stages before the amplifier is in full saturation. The amplifier achieves a maximum gain of 14.31 dB and is optimized for the 5G low-band frequency range from 600 MHz to 1 GHz.

Key metrics of multistage power amplifiers - such as efficiency, linearity, and bandwidth - are strongly influenced by both interstage matching networks (ISMNs) and, in some cases, the nonlinear input impedances of transistors. This work presents a wideband direct matching technique that derives linear RC networks from nonlinear load-pull simulations, providing an intuitive framework to accelerate ISMN design and analysis, while accounting for nonlinear input behavior. A dual-stage Infineon GaN-on-Si demonstrator operating at 6.8 GHz was designed and measured, showing good agreement with simulation and demonstrating the technique's value in guiding the design process.