We present a photoreceiver assembly optimized through comprehensive modeling of the photodiode (PD), the transimpedance amplifier (TIA), and their interconnection. This allows an early and accurate optical signal-to-noise ratio (OSNR) prediction during the TIA design. Fabricated in a $0.5-\mu \mathrm{m}$ InP DHBT technology, the standalone TIA achieves a $59-\text{dB} \Omega$ transimpedance gain and a $70-\text{GHz}$ electrical bandwidth, supporting PAM-4 operation up to 100 GBd without digital signal processing. When wire-bonded to a 50 GHz PD, the photoreceiver exhibits a flat electro-optical response with $\mathbf{5 5 ~ G H z}$ of bandwidth. Open PAM-4 eye diagram is demonstrated up to 112 GBd with a $1.56 \text{pJ} /$ bit efficiency, using a 6 -tap off-line feed-forward equalizer. High linearity is obtained, with a 1 -dB gain compression point reached at 3.5 dBm input optical power, corresponding to a $650-\text{mV}$ electrical output swing. These results pave the way to beyond-112-GBd direct-detection optical transceivers.

In this article, we report on the design and characterization of InP-DHBT analog multiplexer (AMUX)-driver integrated circuits (ICs) for next generation >= 200 Gbaud (GBd) metro/long-haul optical transceivers. We show that the transimpedance stage (TIS) loading of the AMUX selecting cell provides superior gainxbandwidth and linearity performances with respect to the commonly used resistive and cascode loads. Moreover, the driving clock amplitude and tail current of the selecting core are shown to be key parameters for the AMUX-driver design. The AMUX-drivers with TIS loading are fabricated in the III-V Lab's InP DHBT process, showing up to 200-GSa/s sampling rate, without any support of DSP. At 100 GSa/s and 2.4 Vppd of PAM-4 output swing, the highest AMUX FoM is obtained. To the best of the authors' knowledge, these are the highest performances reported to date for an AMUX(driver). Additionally, an AMUX-driver chip is assembled with a TFLN modulator, demonstrating an E/O bandwidth in excess of 85 GHz, while supporting the generation of 100-GBd PAM-4 optical signals, without DSP or active cooling.

This paper reports on key considerations for analog multiplexers (AMUX) implementation in next generation >200-GBd coherent optical TRx. The impact of Nyquist Pulse Shaping and clock jitter on the AMUX SNDR is studied up to 280 GBd.

In this article, we report on the modeling, design, and characterization of indium phosphide (InP) double heterojunction bipolar transistor (DHBT) devices and integrated circuits (ICs) for next-generation optical communications. Critical aspects of transistors' modeling and their influence on the IC design are detailed, as well as the design and characterization of a lumped linear modulator driver featuring a 3-Vppd four-level pulse-amplitude modulation (PAM-4) output swing at 90 GBaud (GBd). In particular, we propose an electromagnetic (EM) simulation-based parasitic extraction method of the DHBT access structures, to refine the DHBT and IC performance prediction accuracy. It is shown to provide a better estimation of a canonical cascode gain and mu stability factor at millimeterwave frequencies, as well as a better estimation of the driver IC gain in the 50-110 GHz frequency range. Furthermore, a highfrequency gain boosting (self-peaking) topology, based upon an emitter-degenerated paralleled-transistor cascode configuration, is analyzed using a simplified transistor model and leveraged to enhance the linear driver output-stage gain-bandwidth product with controlled amount of peaking gain. This self-peaking technique is shown to be inherent to cascode structures and can therefore be used with other technologies, with no added design complexity. The driver IC was implemented in a 0.5-mu m InP-DHBT technology and features a bandwidth well in excess of 110 GHz, with 13 dB of peaking gain at 95 GHz. Besides, it achieves a 9.1-dBm single-ended output power at 1 dB of gain compression and a 2.7% root-mean-square total harmonic distortion (rms-THD) at a 3-Vppd output swing. The driver power consumption is 0.67 W, which is among the lowest in the state of the art and shows a 1.5-GBd driver figure of merit (FoM). To the best of our knowledge, this driver achieves the highest >= 64 GBd PAM-4 performances reported to date, without digital signal processing (DSP) or postprocessing.

Most photoreceivers' front ends rely on an assembly of a photodiode (PD) and a transimpedance amplifier (TIA) to convert the received optical signal into an amplified electrical one. However, ensuring sufficient electro-optical bandwidth, signal-to-noise ratio, and linearity for future Tb/s-class transmitters is challenging as the PD-TIA interconnect becomes a significant issue. We report on an optimization methodology of the front end's Electro-Optical Response (EOR) in tuning the TIA's input impedance to eliminate the resonances originating from the interconnection. We also discuss the importance of the photodiode and PD-TIA interface modeling for the optimization process. After adjustment, the front end achieves a 67-GHz Butterworth-like simulated electro-optical response, with 23 GHz bandwidth control and clear 112-GBd PAM-4 eye-opening. With the proposed method, the front end demonstrates a high resilience to a +/-30% interconnection inductance variation.

In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (<15 μm).

In this paper, we present important challenges in modern optical networks generated by a skyrocketing traffic demand growth. We present the recent evolutions in hardware and software used for optical transmission. Semiconductor technologies for high-speed ICs and examples of circuit design and realizations are discussed. Finally, we present the key and recent system experiments for new generations transceiver developments.

In this paper, a low-loss interconnect strategy for InP integrated circuits operating above 100 GHz is proposed. The interconnect strategy is based upon finite-ground elevated coplanar waveguide (FG-ECPW) structures and requires no through-substrate vias (TSVs) or backside processing. To minimize the reflection losses at the FG-ECPW discontinuities, the ground bridge parasitics are compensated leading to a seamless transmission characteristic through FG-ECPW structures such as Tee-junctions, bends and crosses. The compensated FG-ECPW interconnects have been implemented in a high-speed, mixed-signal InP DHBT technology from III-V Lab. A compensated FG-ECPW meandered line with an accumulated length of 1.65 mm shows a resonance free, single-mode transmission characteristic with an average insertion loss of 2.4 dB in the full D-band from 110-170 GHz. The measured improvement in insertion loss is 3.7 dB at 170 GHz over a similar noncompensated FG-ECPW meandered line.

In this article, we report on the generation of 100-GBd (200-Gb/s) 4-level pulse-amplitude modulation (PAM-4) optical signal, without any support of digital signal processing (DSP) nor off-line equalisation. This is achieved in using an uncooled indium phosphide (InP) analog-multiplexer (AMUX)-driver and a thin film lithium niobate (TFLN) Mach-Zehnder modulator (MZM) assembly, with a -3-dB electro-optical bandwidth in excess of 85 GHz. This result paves the way for low-power DSP-free beyond-1-Tb/s transceivers for next generation optical communication systems and 6G applications. We also present the design and characterisation of the AMUX-driver integrated circuit (IC). The InP-DHBT IC shows a 2-Vppd output swing at 100 GBd in PAM-4 while operating at a 100-GSa/s sampling-rate.

We propose a novel co-packaged optical transceiver architecture capable of operating at 112 Gbaud per lane and scalable to 1.6 Tb/s capacity and beyond for next generation 51.2T and 102.4T digital switches.

In this paper, we report on the design, optimisation and and electrical measurements of a PAM-4 DAC-driver fabricated in 0.7-μm InP/GaAsSb DHBT technology, with the capability to directly drive an electro-optical modulator. Circuit measurements in PAM-4 mode show high diagram quality at 90 GBaud (180 Gb/s) with a record 5.5–V pp differential output swing. An over 12-dB gain control capability is shown. Moreover, a record 3.35-V pp output swing is obtained in PAM-4 at 112 GBaud (224 Gb/s). Power consumption is 1.1 and 0.6 W for two operating symbol-rates respectively.

"Type-II" InP/GaAsSb DHBTs are the first non-GaInAs -based transistors to show oscillation frequencies > 1 THz with the associated benefits of higher breakdown voltages, low power dissipation, and superior linearity and scaling characteristics. Whereas no large-signal characterization of THz transistors is found in the literature, THz InP/GaAsSb DHBTs display attractive 94 GHz load-pull characteristics, and less aggressively scaled devices achieve record saturated output power and output power density per unit emitter area. The physical advantages of Type-II InP/GaAsSb are reviewed here. Beyond impressive analog small/large-signal performance metrics, we report a record mixed-signal performance for a PAM-4 DAC-driver designed and fabricated at III-V Lab in a 0.7-μm InP/GaAsSb DHBT technology implemented on epitaxial layers grown at ETHZ. The DAC-driver offers an unprecedented 5.5-Vppd 90-GBd (180 Gb/s) differential output swing with high eye diagram quality and over 12-dB gain control capability at a 1.1-W power consumption, leading to a record 3.1-GBd E/O modulator driver figure-of-merit (FoM). PAM-4 operation at 112-Gb (224 Gb/s) is also demonstrated with 3.35-Vppd and 0.6-W dissipation, also with a record 2.6-GBb E/O FoM. A 110 GHz bandwidth linear driver with a 16.7 dB gain and 0.85-W consumption was also implemented in the same technology, enabling a 4.1-Vppd output swing at 100 Gb/s both in PAM-4 and NRZ signaling. The all-around outstanding performance of InP/GaAsSb DHBTs makes them attractive for a wide variety of analog and mixed-signal circuit blocks used in modern telecommunication applications.

This letter reports on a 108-GHz bandwidth 0.5- $\mu \text{m}$ InP DHBT analog-multiplexer-driver (AMUX-driver). To the best of the authors’ knowledge, this 2:1 AMUX-driver shows unprecedented 1.9-Vppd 160-GSa/s 160-GBd non-return-to-zero (NRZ) and 2.4-Vppd 100-GSa/s 100-GBd PAM-4 output swings, with very high-quality eye diagrams, without any digital signal processing (DSP) or postprocessing. Up to 3.2 Vppd is obtained in NRZ at 100 GBd. The lumped AMUX-driver also shows record 25.7-dB gain and 2.08-THz gain-bandwidth product with 11.1-dB equalizing capabilities at 86.6 GHz.

In this paper, a D-band stacked power amplifier in a 0.7-×m InP DHBT technology is reported. The power amplifier is implemented using a novel finite-ground elevated coplanar waveguide (FG-ECPW) interconnect environment leading to low-loss power combination. A miniaturized Wilkinson power combiner demonstrates a low loss of ~0.5 dB when measured in a back-to-back configuration. A fabricated two-stage two-way combined triple stacked power amplifier demonstrates a small-signal gain of 14.9 dB at 118 GHz and a - 3 dB bandwidth from 111.2 GHz to 130.6 GHz. The amplifier reaches a peak output power of 17 dBm at 120 GHz. The corresponding large-signal power gain is 9 dB and the PAE is 7.2%

In this article, we present the modelling, design and characterization of a 3-Vppd linear-output-swing 90-GBd PAM-4 modulator driver, realised in III-V Lab's in-house 0.5-μm InP DHBT technology (380/520-GHz ${f_{T}/f_{{\max}}}$ , 4.2-V ${BV_{\text{CE0}}}$ ). The driver exhibits 13-dB equalisation capabilities at 95 GHz with a bandwidth well beyond 110 GHz. It features a 0.67-W power consumption, resulting in a 1.5-GBd FoM with good output signal quality. To the best of our knowledge this linear driver shows the highest >64 GBd PAM-4 performance in current state-of-the-art, without DSP nor pre-emphasis. We also report on a newly developed 0.5-μm InP DHBT technology and its modelling using small-value external parasitic EM-simulation extraction, showing improved high-frequency prediction accuracy at circuit level.

Modern IoT and 5G applications are driving the growth of Internet traffic and impose stringent requirements to datacenter operators for keeping pace with the increasing bandwidth and low-latency demands. At the same time, datacenters suffer from increasing number of interconnections dictating the deployment of novel architectures and high-radix switches. The ratification of 400 GbE standard is driving the market of optical transceivers nevertheless, a technology upgrade will be soon necessary to meet the tremendous traffic growth. In this paper, we present the development of 800 Gb/s and 1Tb/s optical transceivers migrating to 100 Gbaud per lane and employing wafer-scale bonding of InP membranes and InP-DHBT electronics as well as advanced co-packaging schemes. The InP membrane platform is also exploited for the development of novel ultra-fast optical space switches based on a modular architecture design for scaling to large number of I/O ports.

Existing transceiver technology inside data centers will soon reach its limits due to the enormous traffic growth rates driven by new, bandwidth-hungry applications. Efforts to develop the next generation of 800Gbps and 1.6Tbps transceivers for intra-DC optical interconnects have already kicked-off to address the demands in traffic, the exhaustion of the ports at the digital switches and the power consumption limitations inherent to the use of many lower capacity modules. The new generation of optical modules must also provide Terabit capacities at low cost, necessitating the use of high-volume manufacturing processes. TERIPHIC is an EU funded R and D project that aims at developing transceiver modules with up to 1.6 Tbps capacity over 16 lanes in duplex fiber and cost less than 1 € per Gbps for distances up to 2 km, utilizing PAM-4 modulation for 100Gbps per lane and high-volume production compatible transceiver designs. At the component level, TERIPHIC will rely on arrays of high-speed electronics, InP Externally Modulated Lasers (EMLs) and InP photodetectors, and at the integration level it will rely on a polymer photonic platform as a host motherboard, leveraging its flexibility and powerful toolbox. A summary of the progress on the TERIPHIC transceiver modules concept, both at the component level and integration level is presented in this paper.