• 学术搜索
  • 科研智能体
    • Research Labs
    • AI 阅读
    • AI 文库
    • 深度研究
    • 学者亮点
  • 学术资源
    • AI2000
    • 期刊/会议
    • 学者库
    • 学术API
      MCP&Skill
    • 溯源树
    • 数据集
  • 知识沉淀
    • 学术空间
订阅小程序
旧版功能
aminer vip
开通会员低至0.73元/天
一次搞定AI科研
立即登录
  • English
  • 联系方式
    IEEE Transactions on Semiconductor Manufacturing

    IEEE Transactions on Semiconductor Manufacturing

    JournalISSN 0894-6507eISSN 1558-2345中科院 工程技术 4区

    年发文量

    研究主题

    论文(2624)

    排序
    1Quantitative 3D Flow Visualization of Conventional Purge Flow Within a Front Opening Unified Pod (FOUP) under Various Wafer-Loading Configurations
    Minjae Song, Donghwan Seo, Juhan Bae, Hoomi Choi, Nuri Lim, Changjun Lee,Han June Park,Wontae Hwang

    As semiconductor manufacturing processes advance to smaller scales, devices become more vulnerable to defects that reduce performance. Wafers transported in front opening unified pods (FOUPs) are exposed to moisture in the airflow from the fan filter unit (FFU) when mounted to the equipment front end module (EFEM). This moisture reacts with airborne molecular contaminants (AMCs), forming harmful particles that cause wafer defects. Therefore, understanding internal FOUP flow structures is crucial for preventing moisture-induced contamination. Three wafer loading configurations, i.e., odd-layer loaded (OLL), top-loaded (TL), and bottom-loaded (BL), were investigated using magnetic resonance velocimetry (MRV) and computational fluid dynamics (CFD). Both qualitative and quantitative analyses were conducted to determine how wafer protection varies with different loading configurations. MRV measurements showed the load port purge (LPP) flow impinging on the FOUP ceiling and forming an outward flow exiting toward the EFEM at the top. Additionally, CFD results showed that the volumetric fraction of LPP flow in the upper region of the FOUP progressively increased over time. Therefore, wafers loaded in the upper region were found to receive enhanced protection against moisture-laden EFEM flow. This work proposes a strategy to protect wafers from defects by optimizing wafer loading configurations.

    2026
    引用
    AI阅读
    加入学术空间
    2Defect Landscape of the Surface-Treated InGaP/Al2O3 Interface for AlInGaP Micro-LEDs
    Paolo La Torraca, Pavel Kirilenko, Rajan Bharti, Muskan Jain, Satish Bonam, Michael F. Miller,Lida Ansari,Farzan Gity,Karim Cherkaoui, Alexander Tonkikh, Dmitry Sizov, Paul Gore,

    The electrically active defects at the InGaP/Al2O3 interface, representative of an AlInGaP red micro‑light‑emitting diodes (micro‑LED) quantum well sidewall, are profiled using planar metal/insulator/semiconductor (MIS) stacks. The planar structure enables a simple, material selective characterization and allows replicating the micro‑LED fabrication surface treatments. Multifrequency capacitance‑voltage (CV) and conductance‑voltage (GV) analysis reveals shallow InGaP traps and Al2O3 border traps. The effect of the surface treatment (no treatment, HCl wet etching, and BCl₃/Ar plasma dry etching) on the detected traps is reported.

    2026
    引用
    AI阅读
    加入学术空间
    3Integrated DoE and Interpretable AI Framework for Multi-level Co-optimization: Overcoming Tradeoff in RF MOSFETs Performance Enhancement
    Yanping Dong, Qiang Cai, Shuang Wang, Kai Xu, Jilong Yang, Wenjing Mu, Haoji Hu, Ziqi Yang, Qiang Cui, Yongyu Wu, Zhiyuan Cheng

    5G/6G communication evolution and Moore’s law scaling impose stringent device–circuit co-optimization, balancing intrinsic device characteristics and circuit performance. We propose a multi-level framework integrating Design of Experiments (DoE), artificial intelligence (AI), and response surface methodology (RSM). At device level, for each device parameter, separate Gradient Boosting Regression (GBR) and Light Gradient Boosting Machine (LightGBM) models are trained on a dataset built from a compact experimental design; their decision boundaries are approximated by an RSM surrogate, yielding interpretable logic that predicts process parameters for target specifications. At cross-platform level (TCAD-to-SPICE), a human–machine approach combining prompt engineering with the DeepSeek large language model assists in generating data-transfer scripts, accelerating SPICE parameter extraction and circuit simulation. For N-channel RF MOSFETs, we co-optimize cutoff frequency (fT), breakdown voltage (BVDS), off-state current (Ioff), and saturation drain current (Id(sat)) using TCAD, extract BSIM4 parameters, and validate with class-AB power amplifiers. Compared to industry benchmarks, the framework improves Id(sat) by 32.8% to 797 μA/μm without compromising fT, BVDS, or Ioff. Device–circuit co-optimization increases RF power gain by 46% without area overhead and improves P1dB at 3.4 GHz by 28%, with negligible third-order intermodulation distortion (IMD3) penalty. These improvements directly benefit 5G/6G coverage. Multi-model comparisons uncover physical principles; this methodology generalizes to multi-level co-optimization.

    2026
    引用
    AI阅读
    加入学术空间
    4Real-time Perception–Diagnosis–Compensation Framework for IC Test Equipment Stability
    Wenfa Zhan, Chen Mi, Xinyi Hu,Xiaoqing Wen

    Integrated-circuit test equipment operates under multiple programs and electrical conditions, making equipment-induced variation difficult to separate from legitimate device and operating-condition variation. This paper presents a revised closed-loop perception–diagnosis–compensation framework for automatic test equipment (ATE) stability management. The framework combines a Gaussian mixture model (GMM) for operating-condition perception, cluster-referenced residual-domain particle-swarm-optimized Kalman filtering (PSO-KF), Spearman-weighted batch indicators, confidence-guided batch re-estimation (CGBR), quadrant diagnosis, and low-confidence retest routing. The complete evaluation uses 44,509 industrial IC test samples with 149 test items and a leakage-free chronological split of 26,705 training, 6,676 validation, and 11,128 testing samples. A two-component full-covariance GMM is selected by BIC. Under batch point stress, validation-calibrated linear drift, and validation-calibrated random walk, confidence-guided diagnosis returns 33/33, 20/22, and 18/22 displaced batches to the clean Q1 diagnostic region, corresponding to 100%, 90.9%, and 81.8% diagnostic recovery. Measurement-level RMSE reductions remain moderate at 0.62%, 2.27%, and 3.14%, respectively. The results therefore support improved diagnostic consistency rather than direct production-yield recovery. Low-confidence cases remain subject to retest, and no false-pass, defect-coverage, or outgoing-quality claim is made.

    2026
    引用
    AI阅读
    加入学术空间
    5Neural-Network-based Plasma Etch Rate Optimization: Comparative Strategies and Process-Model Validation
    Prakash R. Kota, Rohan P. Kota

    This work presents a comparative framework for target-driven plasma etch-rate optimization using a neural-network process surrogate trained on physics-inspired synthetic data incorporating sample-level noise and batch drift across seven process variables. The surrogate achieved a test coefficient of determination of R2 = 0.990. Quantitative comparison with first-order linear and quadratic-plus-interaction models yielded test R2 values of 0.676 and 0.920, respectively, supporting the use of a nonlinear surrogate for the modeled response. Four optimization strategies, differential evolution (DE), particle swarm optimization (PSO), Gaussian-process Bayesian optimization (BO/GP), and limited-memory Broyden-Fletcher-Goldfarb-Shanno with bounds (L-BFGS-B), were evaluated for nine target etch rates from 50 to 450 Å/min. L-BFGS-B matched all targets to numerical precision at the reported resolution with a mean optimization time of 0.075 s, while PSO provided the strongest derivative-free performance, with a mean absolute optimization error of 0.264 Å/min and mean time of 0.315 s. Each optimized recipe was then independently evaluated using the deterministic process model to distinguish surrogate-level target matching from modeled-process performance. Despite near-zero surrogate-level error, L-BFGS-B exhibited a mean process-model validation error of 13.646 Å/min, demonstrating that increasingly precise surrogate optimization does not necessarily yield proportionally improved process-level accuracy. The results identify surrogate fidelity as an important limiting factor once the inverse optimization problem is solved with high accuracy and support a modular framework for rapid plasma-etch recipe optimization and eventual closed-loop process control.

    2026
    引用
    AI阅读
    加入学术空间
    立即登录,查看全部 2624 篇论文

    高被引作者

    作者引用发文
    Costas J. Spanos142125
    Duane Boning122728
    Chang Ouk Kim113219
    Reha Uzsoy99322
    David A. Dornfeld9375
    Mengchu Zhou90615
    Jianfeng Luo8973
    Gary Stephen May80221
    Naiqi Wu76612
    Lawrence M. Wein7602

    高产作者

    作者引用发文
    Anthony Walton38336
    Duane Boning122728
    Costas J. Spanos142125
    Reha Uzsoy99322
    Stewart Smith25021
    Gary Stephen May80221
    Tadahiro Ohmi46520
    Chang Ouk Kim113219
    Chen-Fu Chien70818
    Sang Jeen Hong32918

    相关期刊

    Microelectronics Reliability
    IEEE transactions on components, packaging, and manufacturing technology
    Technical digest. International Electron Devices Meeting
    IEEE Transactions on Device and Materials Reliability
    International Symposium on the Physical and Failure Analysis of Integrated Circuits
    Advanced Semiconductor Manufacturing Conference
    International Symposium on Semiconductor Manufacturing
    International Symposium on Next-Generation Electronics
    China Semiconductor Technology International Conference
    IEEE Electron Devices Technology and Manufacturing Conference