Hardware architectures of neural networks are of interest for many fields and applications. However, the use of fixed and floating point multipliers results in highly complex hardware architectures. In this paper, the Sets-Of-Real-Numbers (SORN) number format is used for feedforward neural network implementations. It is an alternative binary number representation, using a coarse resolution of intervals, which allows ultra fast and low complex computing. Therefore, SORN arithmetic, including multiplications and activation functions, can be implemented using simple Boolean logic. This paper presents two multiplierfree neural network architectures for MNIST classification on FPGA, using a combination of SORN arithmetic and fixed point adders. Compared to half precision floating point implementations, this approach shows an accuracy reduction 0.66 % and 0.39 %, respectively. However, the utilization of hardware resources is significantly reduced. This is particularly evident in an LUT reduction of 87.8 % and 91.4 % and no usage of DSPs. Furthermore, the throughput in fps is increased by factor 20.4 and 15.98, respectively.

In this paper, a novel computation scheme of the cross-correlation for seismocardiography (SCG) peak detection in resource-constrained systems is proposed. As cost-optimized FPGAs are usually considered in this scope that contain only a small number of DSPs, the excessive use of multipliers quickly exceeds the available fabric resources. To overcome this drawback, Sets-Of-Real-Numbers (SORNs) are taken into account, which generally leads to a significant reduction of complexity at the cost of precision impairments. For evaluation, cross-correlation hardware architecture is implemented in VHDL considering SORN-based multipliers into account and compared to standard fixed-point. The results show a reduction in complexity for LUTs of up to 46 %, highlighting our approach as a feasible solution for resource-constrained systems.

In this work, a novel signal processing approach for the efficient computation of the cross-correlation operator on low-complexity FPGAs is presented. Sets-Of-Real-Numbers (SORNs) arithmetic is exploited to build resource-efficient multipliers that are carefully injected into the hardware architecture. By this measure, a significant decrease of arithmetic hardware requirements is achieved. Especially, in the scope of low-complexity FPGAs, this depicts an enormous advantage, as these devices usually only have a few or even no specific arithmetic hardware accelerators, such as DSP blocks, at all. In order to smoothly integrate these special multipliers, additional conversion functions are needed to handle the number format transformation between SORNs and the fixed-point (FxD) data representation. For the evaluation, several cross-correlation-related hardware architectures with different number formats, data types, and multipliers are taken into account. Out of this, the proposed SORN-based implementation turns out to achieve extremely high performance regarding the resulting signal quality. In terms of the resource utilization, it clearly outperforms the traditional FxD-based architectures. Hence, SORN-based multipliers identify as a powerful extension for calculating the cross-correlation on low-complexity FPGAs.

The Sets Of Real Numbers (SORN) format is a derivation of the universal numbers (unums) and represents an interval-based, low precision number format. It relies on lookup table (LUT) arithmetic, which can be implemented as ROM-like logic circuits. Previous works have evaluated the format for different use cases and applications, mostly under the assumption that the format can only be applied efficiently for bitwidths below 20 bit, because of the increasing complexity of the LUTs. This work evaluates on this assumption by implementing SORN addition and multiplication for different SORN datatypes and bitwidths between 5 and 31 bit, and comparing the resulting hardware circuits to standard integer implementations. The findings in this work show that SORN arithmetic actually scales quite well with bitwidth and mostly outperforms integer arithmetic in terms of hardware measures. Solely the area requirements of the SORN addition modules are higher than for integer designs of same bitwidth, whereas for multiplication a significant area reduction of up to 80% can be achieved. Further, the SORN modules are at least twice as fast as integer, and reduce the power consumption by up to 50% and 97% for addition and multiplication, respectively.

In this paper a novel approach for the efficient computation of the cross-correlation operator is presented, targeting Low-Complexity FPGAs. To keep the signal processing effort of the required complex operators low, Sets-of-Real-Numbers (SORN) arithmetic is considered. For the underlying datatype, a non-uniform interval segmentation scheme is applied, leading to further improvements in terms of algorithmic performance. The feasibility of our approach is demonstrated on the GateMate CCGM1A1 FPGA, highlighting a hybrid SORN-based cross-correlation to be a powerful approach for resource constrained systems.

The Sets Of Real Numbers (SORN) format is an interval-based number representation to perform fast and low-complex arithmetic operations. Since the implemented arithmetic is based on lookup tables, the applied SORN datatypes are not standardized and can be highly application specific. Because the formats precision is rather low in general, the evaluation of suitable SORN datatypes is one of the major challenges when applying the format, since not all datatypes guarantee sufficient results for the implemented algorithms. Therefore, this paper presents an algorithmic approach to determine the optimized interval distribution for a SORN datatype for specific applications. The Adaptive Interval Segmentation (AIS) algorithm is gradient based and applies directional nested intervals to adapt a floating point functionality by SORN arithmetic. This approach is used to evaluate SORN datatypes for Hybrid SORN k-Nearest Neighbor (kNN) classification. For the MNIST dataset, the AIS algorithm provides seven SORN datatypes that show better classification results for Hybrid SORN kNN classification, compared to floating point implementations. This is particular evident in a four and a five bit SORN datatype leading to an accuracy increase of 0.24% and 0.26%, respectively.

In this paper, a new hardware-friendly implementation of a Support Vector Machine (SVM) classifier using the radial basis function (RBF) kernel is presented. It is based on Sets-Of-Real-Numbers (SORN), an interval based number format that allows fast and low complex computing, while providing correct results based on interval arithmetic. For the proposed Hybrid SORN SVM implementation a combination of SORN and fixed point (FxD) representations is used to provide high classification accuracy on low computational complexity. The hardware architecture is implemented on an FPGA board using a 14 bit SORN datatype combined with a 16 bit FxD representation for Euclidean distance calculation, showing an accuracy of 97.71% for the full MNIST dataset, which is only 0.9% below floating point. In addition to RBF kernel, a new SORN-friendly kernel is presented. For this architecture an 18 bit SORN datatype combined with 16 bit FxD is used. Compared to the Hybrid SORN RBF kernel, it consumes less hardware resources including no DSPs, while only increasing the classification error by 0.45%.

Space Mass Memories remain a key component of the data handling system within space missions like earth observation or space exploration. Current and future solid state mass memories are based on NAND flash devices. Growing demands in capacity and throughput as well as technological developments in the commercial memory sector are driving the transition to modern 3D NAND flash devices instead of currently wildly used planar NAND Flash. Equipment level bit error rate estimation considering the different operational modes 3D NAND offers (SLC/TLC) is crucial for satellite end-to-end data integrity performance as well as memory partition design. Therefore this paper presents a case study for the design of a mass memory partition architecture considering the bit error rate of the NAND Flash partition as the superior design driver. Component type, EDAC scheme, NAND Flash operation mode, radiation environment and storage time are explored and their contribution to the resulting system bit error rate is explained.

In this paper a comprehensive overview about State-of-the-Art Space-Grade FPGA and SoC-FPGA platforms from AMD, Microchip, NanoXlore and Frontgrade is presented. To this end, a resource-optimized LEON3 soft-core processor system is taken into account as a core design. For evaluation, resource utilization, achievable operating frequency, power consumption as well as radiation performance are taken into account. The results clearly point out the strengths and weaknesses of all space-grade FPGAs selected as well as it helps in the assessment and selection of the optimal candidate for upcoming space applications.

Modern satellites carry increasingly complex and potent payload systems that produce valuable data for scientific or commercial purposes. These payloads generate high amounts of data in short timeframes which commonly exceeds the capacity of the available downlink channels. This, coupled with sparse contact windows to the ground station, necessitates a way to store payload data on-board for later transmission to ground. Therefore, mass memory units are key components of modern observation satellites. They provide the capability to store and retrieve payload data as well as housekeeping data generated on the satellite. In this paper the current status of a high-performance but reliable MMU development for next generation satellite systems based on a Microchip RTG4 and a Xilinx Versal FPGA is presented. The proposed design will reach data rates up to 20 Gbit s − 1 with a storage capacity of more than 48 Tbit. To this end the architectural design implementation details are shown.

The Sets-of-Real-Numbers (SORN) format for digital arithmetic and signal processing represents real numbers with small sets of exact values and intervals, enabling low-complex and fast computing of arithmetic operations. The format derives from the universal numbers (unum) and has already proven to be a valuable alternative to legacy formats like fixed point or floating point. The main challenge of SORN arithmetic is degenerating accuracy due to increasing intervals widths, which is tackled in this work with the proposal of fused SORN arithmetic for the three-input operations addition, multiplication and multiply-add, as well as the three-input hypot function. Evaluations on accuracy and hardware performance for different SORN datatypes show that accuracy improvements of up to 60 % can be achieved, along with moderate to high hardware complexity increases. In some cases even improvements for both accuracy and hardware performance can be achieved.

Low power (LP) FPGAs are increasingly used in small embedded systems and sensors as processing units or accelerators. To bring the energy efficiency of these FPGAs to a new level, this paper propagates the utilization of undervolting. First, the development and evaluation of a precise and reliable testbench for automated undervolting tests is presented. Second, a comprehensive feasibility study including 5 DUTs shows devicespecific differences, correlations between absolute minimum voltages, signal propagation delays and also the influence of temperature. Depending on the configuration of the FPGA, voltages can be reduced by up to 71.6% while power dissipation is 3× up to 24.3× lower for complex and simple structures, respectively.

DDR4-SDRAMs are key components widely used in modern computing systems on ground and in future space applications, where the sensitivity to ionizing radiation effects and the corresponding data integrity performance is of special interest. In this paper, an example DDR4-SDRAM buffer memory partition inside a high-performance mass memory system is described. For this buffer, two different EDAC implementations, which are Reed-Solomon single-symbol-error-correction and Reed-Solomon double-symbol-error-correction are compared in terms of data integrity performance. This comparison is based on the word error probabilities taking into account DDR4-SDRAM component specific single event effects and possible mitigation such as scrubbing and power cycling. The approach described in this work quantifies the design decision for a certain EDAC architecture as well as highlighting the impact of design parameters such as scrubbing and power cycling periods.

This paper presents a new approach for support vector filtering to accelerate the training process of support vector machines (SVMs). It is based on the Sets-of-Real-Numbers (SORN) number format, which provides low complex and ultra fast computing. SORNs are an interval based binary number format, showing promising results for complex arithmetic operations, e.g. multiplication or fused multiply-add. To apply SORNs to high dimensional vector arithmetic, a combination of SORN arithmetic and fixed-point adder trees is used. This Hybrid SORN approach combines the advantages of SORNs, concerning reduction of computational costs and time, and fixed point adders in terms of precision. A Hybrid SORN support vector filtering architecture is implemented on an FPGA board with Zynq 7000 XC7Z100 SoC and evaluated for the MNIST dataset. It can be considered as hardware accelerator, reducing the training time by factor 1.38 for one-versus-rest and 2.65 for one-versus-one SVM implementation.

Low power (LP) FPGAs are increasingly used in small embedded systems and sensors as processing units or accelerators. To bring the energy efficiency of these FPGAs to a new level, this paper propagates the utilization of undervolting.

In this paper a new implementation of the k-Nearest Neighbor algorithm (kNN) is presented. The approach is based on the Sets-of-Real-Numbers (SORN) representation. SORNs are an interval-based binary number representation providing ultra fast and low complex arithmetic operations. The proposed approach combines the advantages of SORN (complexity) and fixed point representations (precision) to provide high dimensional vector arithmetic operations with high precision. This Hybrid SORN approach is used to implement a low-complexity kNN architecture, introduced as Hybrid SORN kNN. The proposed design is implemented on an FPGA board with Zynq 7000 XC7Z100 SoC and verified with the MNIST dataset. To achieve the data transfer to the FPGA for the complete MNIST dataset, an AXI Direct Memory Access (DMA) IP-Core to access an SD card is used. The proposed architecture provides promising results since the validation error is significantly lower compared to floating point implementations. The hardware utilization shows an LUT reduction of 39.2% compared to a fixed point implementation.

In this paper a novel hardware architecture for high-accuracy and near-sensor BCG complex recognition is presented. Main contribution of our work is the implementation of an adaptive method for J-wave peak detection on FPGA enabling reliable online waveform monitoring. Also, to further increase the overall signal quality, Chebyshev-based filtering is installed, leading to a smoother signal progression. The evaluation results highlight our approach as a well suited solution for online BCG complex recognition in resource constraint environments, as detection rates between 95.31% and 100% can be achieved considering human bodies in a resting position.

This paper introduces Wireless Compose-2 (WICO2), which is an experiment for the International Space Station (ISS) in order to demonstrate the provision of a flexible and adaptable wireless network infrastructure integrated into a commodity item to conduct and execute low-power, low-weight and wireless experiments in the scientific and medical domain. Recent work revealed a great potential in utilizing Wireless Sensor Network (WSN) in space habitats; however, the focus was only placed on sensing in the narrowband Industrial Scientific and Medical (ISM) 2.45 GHz band. This work extends these capabilities by utilizing Impulse Radio Ultra Wideband (IR-UWB) for ranging and evaluates the use of internal light sources for energy harvesting to drive the sensor nodes. The focus of the WICO2 experiment is on the operation of the scientific experiment Ballistocardiography for Extraterrestrial Applications and long-Term missions (BEAT), which is a demonstration of novel Ballistocardiography (BCG) sensors to monitor important cardiovascular parameters in a microgravity environment. Integrated in a Smart-Shirt, it will form a Body Area Network and make use of the IR-UWB communication to transmit the data to the network. This paper describes the concept and pre-flight test results to demonstrate the correct function, usability and performance of WICO2.

Comprehensive health monitoring is highly relevant for the safety of manned spaced missions. Ballistocardiography (BCG) is a method for providing information of the heart physiology by measuring accelerations on the body surface that are caused by forwarded heart and blood movements in the vascular system. In order to provide a sensor system with a high signal quality, this paper presents differential BCG sensing at the system level for digital accelerometers and its integration into a sensing system. The system is part of a running experiment of the Cosmic Kiss mission on the International Space Station (ISS). Compared to single sensor solutions, the noise power scales down to about 50%, the Signal to Noise Ratio (SNR) is increased by a factor of 1.87 and the BCG signal variability especially improves for diastole area. Furthermore, by exploiting differential sensing techniques, both high reliability is achieved and common mode interference is mitigated, which is of high importance within the scope of space applications. Beside the presentation of the entire wireless sensor system including differential sensing approach, pre-processing unit and Ultra Wideband (UWB) communication module, results of the pre-flight tests show the performance of the system as well as the suitability for targeted mission.

This paper describes the protocol of the microgravity experiment BEAT (Ballistocardiography for Extraterrestrial Applications and Long-Term Missions). The current study makes use of signal acquisition of cardiac parameters with a high-precision Ballistocardiography (BCG)/Seismocardiography (SCG) measurement system, which is integrated in a smart shirt (SmartTex). The goal is to evaluate the feasibility of this concept for continuous wearable monitoring and wireless data transfer. BEAT is part of the "Wireless Compose-2" (WICO2) project deployed on the International Space Station (ISS) that will provide wireless network infrastructure for scientific, localization and medical experiments.