The nanoAUV is a fully autonomous and miniaturised underwater vehicle developed for under-ice and subglacial lake exploration. The vehicle is part of the TRIPLE project, which additionally comprises of an ice melting probe and a launch and recovery system. The nanoAUV is designed to navigate autonomously and carry a variety of sensors and systems for environmental sampling and data collection. This paper describes the system development, including sensor integration for under-ice and subglacial lake exploration in Polar regions. The paper also presents initial results of tests and evaluations of the nanoAUV and provides an outlook on a forthcoming mission to explore the underside of the ice shelf near Neumayer Station III research station, Weddell Sea, Antarctica.

In-situ observation of the deep-sea floor is a fundamental need for marine sciences and ecosystem monitoring. This work proposes a novel robotic approach for benthic observations in the deep sea using underwater gliders. The glider is equipped with a downward looking camera system to acquire high resolution optical images of the seafloor. The system works fully autonomous and has the potential for long-endurance missions at low deployment costs. Key factors for long battery lifetime are a low power consumption during idle phases, a timely activation of the main imaging system and an efficient lighting setup. The results of our initial trials at sea using a 1000m glider show the applicability of the approach for marine science applications. We achieved optical image quality utilizable for seafloor classification and 3D reconstruction of underwater objects. Keeping the vertical zig-zag motion of underwater gliders in mind, our findings substantiate the feasibility of multi-week seafloor observation missions at long operating ranges.

Sea ice is subject to continual change. It arises as seawater freezes, and is driven and deformed by winds, currents, ocean waves and temperature fluctuations. To observe the sea ice and its motion on a broad scale, Synthetic Aperture Radar (SAR) satellites are well suited, particularly as they provide images of land and frozen waters though clouds and regardless of solar illumination. In this paper, we present a software processor that is intended for the retrieval of high-resolution sea ice drift vector fields from pairs of subsequent, co-located SAR images. The core of the sea ice drift tracking algorithm is the well-known phase correlation technique executed hierarchically in a multiscale Gaussian pyramid. We explore the capabilities of the algorithm with a SAR image time series taken by the European satellite mission Sentinel-1 over the Arctic Ocean offshore close to Cape Morris Jesup during December 2021, when the ocean showed a closed cover of mainly multiyear ice. The retrieved sea ice drift vectors are validated with buoy data. In addition, we applied sea ice type classification on the SAR image series using the drift tracking algorithm for fusing classification results of the individual, subsequent SAR images. In so doing, we overcome inconsistent classification results and overall increase stability and reliability of the classification results.

The functionality of electronic circuits can be seriously impaired by the occurrence of dynamic hardware faults. Particularly, for digital ultra low-power systems, a reduced safety margin can increase the probability of dynamic failures. This work investigates a deep learning approach to mitigate dynamic fault impact for artificial neural networks. As a theoretic use case, image compression by means of a deep autoencoder is considered. The evaluation shows a linear dependency of the test loss to the fault injection rate during testing. If the number of training epochs is sufficiently large, our approach shows more than 2% reduction of the test loss compared to a baseline network without the need of additional hardware. At the absence of faults during testing, our approach also decreases the test loss compared to reference networks.

Autonomous underwater vehicles have increasing demands for computer vision capabilities. As an example, marine ecosystem observation will strongly benefit from real-time analysis of acquired images. However, the complexity of computer vision algorithms and the vast amount of data from still images or video induces serious challenges for the limited energy budget of the vehicles. We propose the extensive employment of field programmable gate array for the energy efficient implementation of on-board computer vision tasks. Our case study considers dedicated implementations for particle image velocimetry and stereo depth map estimation. The results show a substantial improvement in energy efficiency while maintaining attainable accuracy compared to a software reference model.

We propose an efficient approach for massive MIMO uplink detection using a tree of QR decomposition modules. The receive data is split onto the input modules and reduced during processing. The data rate does not increase while baseband data is combined and forwarded towards the root node of the tree. For the uplink baseband processing of a 128x8 MIMO system a 1.46 speedup is achieved. Our approach improves the applicability and scalability of massive MIMO for wireless industrial communication while requiring very low-latency and jitter.

The radar satellite TerraSAR-X monitors the Earth's surface in a near-polar orbit. To provide the maritime community with up-to-date information on the presence and location of icebergs, the high-resolution radar images provided by the satellite are processed automatically by an image processing chain. A cell-averaging constant false alarm rate detector is used for iceberg detection, which has proven its usefulness for terrestrial object detection already. However, data transmission and processing require an impractical amount of time for real-time operation. In the present work, an FPGA-based hardware prototype of the detection algorithm is proposed, which accelerates image processing by a factor of ten compared to a software implementation and shows potential for further speed-up in the future.

Many-core systems provide abundant computing power for parallel applications. Unfortunately, processor design reaches the so-called utilization-wall (dark silicon). If designers want to achieve a higher performance, their systems need to become more energy-efficient and specialized. This thesis focusses on the hardware optimization of the run-time manager to improve the overall system efficiency. We present a transactionlevel simulation framework for the design-space exploration of hardware-enhanced run-time management. Based on the framework a concrete architecture for hardware-enhanced run-time management has been implemented. The evaluation identifies the crucial output parameters which are affected by the hardwareenhancement and quantifies the benefits compared to state-ofthe-art software approaches.

In this paper, we propose a decentralized feedforward initialization approach for iterative equalization methods, that decomposes a massive MIMO system into multiple smaller subsystems, where successively combining pairs of these systems and their solutions using the Jacobi method results in a high quality initial estimate for a following iterative detection method. In contrast to existing methods, this approach allows a computation of an initial estimate while the Gram matrix and matched filter output vector is not fully available. The BER performances show the effectiveness of this initialization method compared to approaches like maximum-ratio combining at high basestationto- client antenna ratios.

Many-core architectures integrate a large number of comparatively small processing cores into a single chip. However, the high degree of parallelism increases the run-time resource management complexity and overhead. The employment of dedicated hardware enhancements potentially enables a high quality of the resource management while management overhead is mitigated. To exploit the potential of hardware enhancements, we propose a dedicated infrastructure for run-time resource management on homogeneous MIMD many-core processors. For hardware enhanced resource management, a scalable and cluster-based system architecture is implemented. The resulting architecture (DRACON) utilizes message passing based communication, the dedicated infrastructure and hardware accelerators for resource management. A comprehensive evaluation for DRACON and reference architectures is performed using a transaction level simulation framework and dynamic task management as a use case. As benchmarks, synthetic models and task graph models of real-world applications are applied. The results reveal the limited scalability of classical architectures for resource management on many-cores. It is therefore necessary to apply cluster-based or moderately distributed architectures for many-core resource management. Further, the results demonstrate a significant performance improvement for the DRACON architecture at a number of hundreds of processing cores. Our evaluations show that DRACON generally outperforms software-only run-time management on many-core and achieves a performance improvement of up to 15.21% for single-program and more than 6% for mixed workloads.

Massive MIMO systems have become more popular in wireless communications due to their improved spectral efficiency compared to existing small-scale MIMO systems. However, current estimation methodes take too long for larger numbers of antennas. In this paper, a near-optimal iterative linear signal detection for massive MIMO is introduced exploiting the random projection method to approximate the channel matrix in a significantly lower dimensional space. This is then used as a preconditioner in the conjugate gradient least squares algorithm to enhance the convergence rate. For evaluation, different scenarios of spatial correlation in a massive MIMO system are considered. In contrast to other low-complexity signal detectors, our approach achieves excellent results in terms of robustness and determined latency.

The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. The integration of dedicated hardware to enhance the performance of the run-time management system is gaining an increasing importance. But the design of a run-time manager for many-core generally suffers from exhaustive evaluation time. Previous works do not address for the required flexibility or do not address for reasonable evaluation time of the simulation framework. We propose the novel simulation framework Agamid to foster the development and evaluation of hardware enhanced run-time management for many-core. Our transaction-level framework performs design point evaluation of hardware enhanced run-time management for many-core at the timescale of seconds. We use a hybrid simulation approach considering the run-time management and the user application at different levels of abstraction. The framework provides a generic run-time manager to compare arbitrary management systems and HW/SW partitionings. The implementation of the run-time manager facilitates direct execution at the host machine and a detailed synchronization model. Agamid applies user application workloads by means of transaction-based task graphs. An extendable system-call interface allows arbitrary interaction between the user application and the run-time management system. The thorough calibration of the RTM timing model enables reasonable approximations of the management overhead. Our evaluation considers the accuracy, wall-time and design space exploration capabilities of Agamid. Our findings substantiate the usefulness to integrate the modeling of the run-time management, hardware architecture and user application into a single transaction-level framework.

The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. However, the design of a many-core run-time manager generally suffers from exhaustive evaluation time. AGAMID is a novel research framework for design space exploration of hardwareenhanced many-core run-time management. The framework uses SystemC/TLM for flexible and productive system modeling while allowing evaluation at the timescale of seconds. We provide a generic run-time manager to compare arbitrary management systems and HW/SW partitioning. Real-world application workloads are applied by means of compact task graphs. The integrated system-call interface enables fast and task-accurate full-system simulation.

Enhancing an electrical NoC with a reconfigurable nano-photonic interconnect architecture contributes to mitigate the bandwidth bottleneck typically found in modern systems. The management of such photonic channels, however, complicates the control of the network and deteriorates its predictability. For the autonomous management of the photonic links with full predictability, this work proposes a hybrid architecture, where several distributed hardware agents connected with a TDMA-based electrical NoC with a photonic layer. These agents provide a dynamic (at run-time) configuration infrastructure for the photonic switches; thanks to the bounded delay of the TDMA-NoC, the configuration overhead can be accurately predicted and the quality-of-service guaranteed. Furthermore, the architecture is highly scalable due to the predictable, autonomous, and decentralised administration of the links. This paper reports an architectural evaluation which combines a thorough analysis of the hardware cost at the gate level and a functional validation of the improved predictability; the results confirm the suitability of the approach.

The increasing parallelism of many-core systems demands for efficient strategies for the run-time system management. Due to the large number of cores the management overhead has a rising impact to the overall system performance. This work analyzes a clustered infrastructure of dedicated hardware nodes to manage a homogeneous many-core system. The hardware nodes implement a message passing protocol and perform the task mapping and synchronization at run-time. To make meaningful mapping decisions, the global management nodes employ a workload status communication mechanism. This paper discusses the design-space of the dedicated infrastructure by means of task mapping use-cases and a parallel benchmark including application-interference. We evaluate the architecture in terms of application speedup and analyze the mechanism for the status communication. A comparison versus centralized and fully-distributed configurations demonstrates the reduction of the computation and communication management overhead for our approach.

Many-core systems provide abundant computing power for parallel applications. The run-time manager of an embedded system has to efficiently exploit the available resources while guaranteeing a high responsiveness. We propose a dedicated hardware infrastructure to improve the scalability and responsiveness of a run-time task manager. The hardware enhancements constitute a hierarchy of global and local control nodes which communicate by means of message passing. The global nodes facilitate a distributed task manager which performs the task scheduling and a flexible task synchronization scheme at run-time. A low-latency interface between the run-time system and the processing cores is provided by the local nodes.Based on simulations using a SystemC model, we demonstrate the advantages of our approach in terms of application performance. The design feasibility is substantiated by means of gate-level analysis. We compare our results against state-of-the-art software and hardware-based run-time management systems.

Optical network-on-chips (oNoCs) are a promising candidate to replace electrical NoCs in many-core systems. Nanophotonic components provide high bandwidth and short transmission delay but they are very sensitive to the temperature. Temperature gradients are typically found on many-core systems. The precise reconstruction of the core's temperature and the prediction of its evolution are an inevitable requirement for an effective thermal management in oNoCs. In this work we present the first distributed and autonomous thermal monitoring infrastructure for oNoCs. It copes with the intrinsic temperature sensor's noise, provides accurate thermal predictions, and requires low communication overhead. Our approach combines Kalman filters, linear predictors, local data and global transmission to achieve an efficient implementation. The work reports a thorough analysis at the gate-level of the area overhead incurred by the communication and computation sub-modules. It shows the practicability of the approach. Further, experimental results for a 16-core SoC demonstrate that our prediction model is able to reduce by more than 92% the communication requirements of the monitoring infrastructure.

The increasing number of processing elements on embedded many-cores gives novel challenges for the chip design. Dedicated hardware has become an important feature to support the applied operating system and to improve the overall system efficiency. Since evaluation of novel architectures requires time expensive simulations or prototyping, transaction-level analysis gives an appropriate tool for early design stage evaluation. This work proposes a transaction-level framework for simulating hardware-enhanced many-core operating systems. The framework allows the design space exploration of the hardware and software architecture and uses a trace-based task description language including a customized interface for system calls.

The increasing requirements for bandwidth and quality-of-service motivate the use of parallel interconnect architectures with several degrees of reconfiguration. This paper presents an IP, called Distributed Channel Management (DCM), to extend existing packet-switched NoCs with a reconfigurable point-to-point network seamlessly, i.e., without the need for any modification on the routers. The configuration of the reconfigurable network takes place dynamically and autonomously, so that the topology can be changed at run time. Furthermore, the architecture is scalable due to the autonomous decentralized administration of the links. The Paper reports a thorough experimental analysis of the overhead of the approach at the gate level that considers different network parameters such as flit size and timing constraints.

The trend for multicore processor architectures indicates an ongoing increase in computing cores per chip. The resulting challenges demand for a revision of the applicability of existing hardware operating systems. We propose a scalable best-effort task scheduler implemented in hardware, which services a homogeneous multiprocessor architecture. The hardware scheduler realizes a master/slave system to maximize available parallelism. Experimental results show the scalability of the hardware scheduler in terms of performance, area and power. A design pattern to generate a hierarchical communication architecture for task management is prospected.