We expand on our work in [1] by demonstrating both Si P- and NMOS finfet transistors monolithically integrated with GaN transistors on 300mm Si(111) wafers using 3D integration. With the Si finfet architecture, we are able to take advantage of the fin orientations of the transferred Si(100) crystal to fabricate both high performance Si P- and NMOS transistors. Furthermore, we demonstrate a variety of GaN transistor innovations, including enhancement (e-mode) and depletion mode (d-mode) GaN NMOS transistor with high ID =1.8mA/μm; GaN Schottky gate transistor producing high saturated power of 20dBm with peak PAE=57% at 28GHz; high performing, low leakage cascode and multi-gate GaN transistors; and GaN Schottky diodes with ultra-low COFF for ESD protection, all integrated on 300mm Si(111) wafer.

For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L G =25nm featuring record high I ON =508 µA/µm at I OFF =100nA/µm and V DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D IT and N IT for s-Si 0.4 Ge 0.6 channel, (b) record high hole mobility= 450 cm 2 /Vs owing to compressive strain imparted by Si 0.7 Ge 0.3 strain relaxed buffer (SRB), (c) low R EXT =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I OFF . Additionally, the impact of operating temperature on GIDL and I OFF is comprehensively studied to prescribe optimal V CC range of operation for this technology.

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) I OFF as low as 100pA/μm (V D =5V, V G =0V), (ii) high I D,max =1.5mA/μm; (iii) R ON as low as 610Ω-μm, significantly better than industry-standard Si transistors at equivalent drain breakdown (BV D ), (iv) excellent RF performance: f T =190GHz, f MAX =300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, R on C off =110fs, and (vi) low noise figure, NF min =1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) L G =65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/μm, and low I off of 150pA/μm at V D =-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.

We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.

A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4th generation high-k metal gate, and 6th-generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.

Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semiconductors), relative to that of FinFET CMOS. The simulation results imply, albeit with complex processing, good scalability and performance for low-power (LP) applications (including static random access memory), defined by minimum viable SOI thickness. However, the scalability for high-performance (HP) applications is limited, but the processing can be simplified. Results for double-gate FinFETs are better, showing good scalability and performance to the end of the ITRS for both HP and LP applications.

Nanoscale double-gate (DG) FinFETs with undoped fin bodies are shown to have threshold voltages (V-t) that can be adjusted for independent I-ON and I-OFF control by allowing limited source/drain (S/D) dopants in the channel. S/D engineering of the lateral doping profile in the extension is proposed as a viable means for effecting such channel doping [as well as gate-S/D (G-S/D) underlap] and, thus, adjusting V-t for optimal I-ON/I-OFF in low-power and high-performance applications of nanoscale-FinFET CMOS. Physics-based device simulations, numerical simulations, and measured current-voltage characteristics are used to demonstrate and support the proposed V-t design approach.

An approach to nanoscale DG FinFET design for LP and HP nanoscale-CMOS applications via S/D engineering [i.e., control of NSD(y)] was proposed, and demonstrated to be viable by device simulations and measurements. The approach exploits the idea of allowing S/D dopants properly distributed in the channel for HP-Vt design. We demonstrated the design approach at the 45nm node. Scaling Lg to Lt10nm, as projected at the end of the SIA roadmap [1], will require sigmaL to be reduced by about a factor of two, which appears feasible with acceptable sensitivities via new processing such as laser annealing.

Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve nanoscale DG CMOS speed substantially.