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The sensitivity of Iithographic process window to global planarity of the inter metal dielectric layers is established in this work. The inter metal dielectric layers, between the metal layers, were prepared by utilizing the H2O2/SiH4 chemistry known as the "Advanced Planarity Layer (APL)". Four degrees of global planarity were tested within the APL process window, utilizing different H2O2 stabilization pressures. SEM cross sections were used to determine the degree of planarity in the CMOS product and at lithographic test structures. The lithographic process window and the effect of the stepper leveling system were defined for typical high and low topographies. The results show a strong link between the lithographic process window to degree of global planarity of the APL. Good global planarity enlarged depth of focus and energy latitude, allowing a wider lithographic process window. Also, in cases of improved APL planarity, the stepper leveling system had only a limited contribution to a Iithographic process window. This control over the: global planarity of the inter metal dielectric layers and the wide lithographic process window that results eliminate the need for CMP at 0.5 mu technology.