The size of the embedded SRAM is steadily increasing in high-end microprocessors like Athlon64/spl trade/ and Opteron/spl trade/. So the demand for small cell footprints and improved stability has become more challenging. We describe how AMD has recognized and addressed the competing aspects of technology scaling and improved stability in the 90nm technology.

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (LGATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

It is important to understand what the floating-body effects are and how they affect device and circuit behavior. In this regard, this article qualitatively explains the device physics underlying DC and transient floating-body effects, clearly implying their influence on circuits, and thereby giving good insight into PD/SOI CMOS design issues. The article also notes special but practical device and circuit designs for controlling floating-body effects, showing through simulation how PD/SOI offers a significant performance advantage over bulk silicon in low-voltage applications, thereby conveying an assurance that reliable SOI CMOS design is feasible.

Historically, body ties have been designed using removal of DC floating-body (FB) effects (e.g., kink, breakdown voltage) as the main criteria. It has been implicitly assumed that the transient FB effects would be minimized too with such a tie. However, such body ties while “suppressing” DC effects, may not necessarily be effective in AC/transient conditions, since the body (dis)charging time constants may be much larger than desired. For example, in a digital SOI CMOS circuit, with the gate switching at a few tens of ps, the efficacy of the body tie may be little or none at all, depending on the response time τB(=RBCB) of the body. Hence, in order to design effective body ties in transients, dynamic (dis)charging effects due to RB and CB in the body must be included