Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique for SOI CMOS transistors. We distinguish between low- and high-temperature stress memorization. Film hardness, stress level, and the order of anneals are found to play an important and partially very different role for these two improvement mechanisms.

Partially depleted (PD) SOI technologies are mature for production of high speed, low power microprocessors. The paper highlights several challenges found during the course of development of a PD 90nm SOI technology. The technology features highly advanced transistors using strained Si and a gate length of sub 45nm with a nine layer low k backend. By optimizing the strained Si process and overall processing we have achieved yield equal than conventional technologies but with higher performance. The technology was developed for the 64bit Opteron and Athlon 64 microprocessors.

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (LGATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.