The commercialization of 4H-SiC MOSFETs will greatly depend on the reliability of gate oxide. Long-term gate oxide reliability and device stability of 1200 V 4H-SiC MOSFETs are being studied, both under the on- and off-states. Device reliability is studied by stressing the device under three conditions: (a) Gate stress - a constant gate voltage of +15 V is applied to the gate at a temperature of 175°C. The forward I-V characteristics and threshold voltage are monitored for device stability, (b) Forward current stress – devices are stressed under a constant drain current of I d = 4 A and V g = 20 V. The devices were allowed to self-heat to a temperature of T sink = 125°C and the I-V curves are monitored with time, and (c) High temperature reverse bias testing at 1200 V and 175°C to study the reliability of the devices in the off-state. Our very first measurements on (a) and (b) show very little variation between the pre-stress and post-stress I-V characteristics and threshold voltage up to 1000 hrs of operation at 175ºC indicating excellent stability of the MOSFETs in the on-state. In addition, high temperature reverse bias stress test looks very promising with the devices showing very little variation in the reverse leakage current with time.

Fabrication and characteristics of high voltage, normally-on JFETs in 4H-SiC are presented. The devices were built on 5×1015 cm−3 doped, 12 µm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 10 mΩ-cm2 and a blocking voltage of 1.8 kV were measured. Device characteristics were measured for temperatures up to 300°C. An increase of specific on-resistance by a factor of 5 and a decrease in transconductance were observed at 300°C, when compared to the value at room temperature. This is due to a decrease in bulk electron mobility at elevated temperature. A slight negative shift in pinch-off voltage was also observed at 300°C. The devices demonstrated robust DC characteristics for temperatures up to 300°C, and stable high temperature inverter operation in a power DC-DC converter application, using these devices, is reported in this paper.

In this paper, static and switching characteristics of a 1200V 4H-SiC BJT at bus voltage of 600V are reported for the first time. Comparison was made between 1200V SiC BJT and 1200V Si IGBT. The experimental data show the SiC BJT have much smaller conduction and switching losses than the Si IGBT. Our previous work showed a large RBSOA of SiC BJT. No second breakdown, which is the most unattractive aspect of the Si BJT, was observed in the 1200V SiC BJT. The results prove that, unlike Si BJTs, BJTs in 4H-SiC are good competitors to Si IGBTs

SiC power devices have very promising future because their ultra low conduction and switching losses and ability of working at high temperatures. SiC MOSFET not only has very low switching loss but also shows no degradation in Rdson at 150°C. In order to achieve ultra low switching loss for SiC BJT, a new drive method is proposed and implemented. These characteristics make SiC power MOSFET/BJT devices attractive for high frequency single phase PFC applications. In this paper, a 1MHz all SiC PFC is designed and evaluated. Experimental results are presented in this paper. These results are also compared with silicon CoolMOS.

High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

The performance and characterization of SiC JFETs and BJTs, used as inverter switching devices, in a 2 kW, high temperature, 33 kHz, 270-28 V DC-DC converter has been accomplished. SiC and Si power devices were characterized in a phase shifted H-bridge converter topology utilizing novel high temperature powdered ferrite transformer material, high temperature ceramic filter capacitors, SiC rectifiers, and 10 oz. 220oC polyimide printed circuit boards. The SiC devices were observed to provide excellent static and dynamic characteristics at temperatures up to 300oC. SiC JFETs were seen to exhibit on-resistance trends consistent with temperature-mobility kinetics and temperature invariant dynamic loss characteristics. SiC BJTs exhibited positive temperature coefficients (TCE) of VCE and negative β TCEs, with only a 2-fold increase in on-resistance at 300oC. Both SiC power devices possessed fast inductive switching characteristics with τon and τoff ~100-150 ns when driving the transformer load. The SiC converter characteristics were compared to Si-MOSFET H-bridge operation, over its functional temperature range (30-230oC), and highlights the superiority of SiC device technology for extreme environment power applications.

Degradation in both current gain and specific on-resistance of fabricated 4H-SiC BJTs have been observed after a short period of operation. In this paper, 1200 V BJTs were stressed and factors that cause the degradation are proposed. The degradation may be attributed to the increase of the surface states density along the SiC/SiO2 interface, which results in an increased surface recombination current and hence the degradation of the SiC BJT.

The reduction in the current gain of SiC BJTs has been observed after operating the devices for as little as 15 minutes. It is accompanied by an increase in the on-resistance of the BJT. The origin of the current gain degradation in the BJTs is investigated. Two possible mechanisms, which may be simultaneously present in the device, are thought to be responsible: (a) increase in the surface recombination particularly in the region between the emitter and the base implant, and (b) bulk recombination in the base due to the generation and growth of stacking faults. Initial observation reveals the presence of stacking faults in the base-emitter region when the device is forward-biased. At the same time, minimizing the effects of recombination from the surface using improved passivation helped in the suppression of the current gain degradation in SiC BJTs.

SiC BJTs show instability in the I-V characteristics after as little as 15 minutes of operation. The current gain reduces, the on-resistance in saturation increases, and the slope of the output characteristics in the active region increases. This degradation in the I-V characteristics continues with many hours of operation. It is speculated that this phenomenon is caused by the growth of stacking faults from certain basal plane dislocations within the base layer of the SiC BJT. Stacking fault growth within the base layer is observed by light emission imaging. The energy for this expansion of the stacking fault comes from the electron-hole recombination in the forward biased base-emitter junction. This results in reduction of the effective minority carrier lifetime, increasing the electron-hole recombination in the base in the immediate vicinity of the stacking fault, leading to a reduction in the current gain. It should be noted that this explanation is only a suggestion with no conclusive proof at this stage.

We report on the development of the first 1 cm x 1 cm SiC Thyristor chip capable of blocking 5 kV. This demonstrates the present quality of the SiC substrate and epitaxial material. A forward drop of 4.1 V at 100 A and 25°C has been measured. The turn-on delay is found to be a strong function of the gate current. At a gate current of 0.5 A, a turn-on delay of 250 ns is observed for an anode to cathode current of 200 A. The turn-on delay reduces to 72 ns for an IG = 1.5 A. The turn-on rise time is a strong function of the anode to cathode voltage, VAK. At VAK =230 V, the turn-on rise-time is 300 ns for IAK =200 A. The rise-time reduces to 26 ns for VAK = 500 V.

Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

In this paper, we report 4H-SiC power DMOSFETs capable of blocking 10 kV. The devices were scaled up to 5 A, which is a factor of 25 increase in device area compared to the previously reported value. The devices utilized 100 mum thick n-type epilayers with a doping concentration of 6 times 1014 cm-3 for drift layers, and a floating guard ring based edge termination structure was used. The gate oxide layer was formed by thermal oxidation at 1175 degC, followed by an NO anneal. A peak effective channel mobility of 13 cm2/Vs was extracted from a test MOSFET with a W/L of 150 mum / 150 mum, built adjacent to the power DMOSFETs. A 4H-SiC DMOSFET with an active area of 0.15 cm showed a specific on-resistance of 111 mOmega-cm2 at room temperature with a gate bias of 15 V. The device shows a leakage current of 3.3 muA, which corresponds to a leakage current density of 11 muA-cm-2 at a drain bias of 10 kV

SiC BJT is a very promising switching power device because of its ability to operate at high temperature. This capability, coupled with ultra low conduction and switching loss, will facilitate very high frequency operation. This will have a significant impact on applications such as PFC where power density is of high interest. In this paper, an all SiC PFC is designed and implemented. In order to achieve ultra low loss, a new drive method is implemented that uses a conventional MOSFET driver to drive the SiC BJT. Based on this method, the turn on and turn off loss of the SiC device can be reduced significantly. Based on the measured loss, the maximum operating frequency of the PFC converter is predicted. Experimental demonstration at 400kHz and 300W is presented in this paper.

4 kV, 10 A bipolar junction transistors have been demonstrated in 4H-SiC. The device conducts 10 A of collector current with a current gain of 34 at room temperature. The current gain reduces to 21 at 300 degC. Under reverse bias, the device is capable of blocking 4.7 kV with 50 muA leakage current. Room temperature switching measurements show a turn-on time of 168 ns and a turn-off time of 106 ns. These devices show some current gain instability, with the gain decreasing by 50% with time under forward stress. Initial observations reveal the presence of stacking faults in the base-emitter region when the device is forward biased

La presente invention concerne des procedes de formation d’une couche d’oxyde sur du carbure de silicium comprenant la croissance thermique d’une couche d’oxyde sur une couche de carbure de silicium et le recuit de la couche d’oxyde dans un environnement contenant du NO a une temperature superieure a 1175 °C, idealement 1300 °C. La couche d’oxyde peut etre recuite dans du NO dans un tube de carbure de silicium qui peut etre recouvert de carbure de silicium. Pour former la couche d’oxyde, on peut proceder a la croissance thermique d’une couche preliminaire d’oxyde sur une couche de carbure de silicium dans du O2 sec, puis reoxyder ladite couche preliminaire d’oxyde dans du O2 humide.

SiC materials and device technology has entered a new era with the commercialization and acceptance of 600 V/10 A and 1200 V/10 A Schottky Barrier Diodes (SBDs) in the marketplace. These diodes are finding applications in the Power Factor Correction (PFC) stage of Switch Mode Power Supplies (SMPS). SiC power MOSFETs with ratings of 800-1200 V up to 10 A will soon be commercially available. The next step is to integrate the SiC MOSFET and Schottky diodes in a power module for PFC and motor control applications. For high temperature applications, greater than 200°C, a bipolar switch such as a SiC BJT offers superior performance over the MOSFETs. The lack of gate oxide in the BJT offers better reliability at such extreme temperatures, in addition to the lowest combined switching and conduction losses.

Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.

For the first time, 4H-SiC RF bipolar junction transistors have been used to produce an output power in excess of 2.1 kW at 425 MHz. For an input pulse width of 2 μs and 1% duty cycle, the power gain at peak output power is 6.3 dB with the collector efficiency and power added efficiency [PAE] being 45% and 35%, respectively, at a collector supply voltage of 75 V in a class C configuration. The package consists of 24 cells (2 chips) having an emitter periphery of approximately 1 inch per cell. Each cell produced a DC current gain (β) of 15 and a common emitter breakdown voltage (BVCEO) greater than 250 V. A peak output power of 87 W per cell was obtained at 425 MHz, as compared to the earlier report of 50 W per cell [1, 2] by using a shorter pulse width and duty cycle.

8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.