This paper reports random telegraph signal (RTS) noise and charge pumping measurements both performed on the selection transistor of a single 16 Mbits dynamic random access memory (DRAM) cell. Hot carrier induced degradation has been evaluated after stress in terms of generation of slow and fast interface traps. Due to the three dimensional design of the DRAM cell, we show how it is possible to scan electrically active defects in different parts of the transistor structure by varying the potential distributions in the DRAM cell. Defect location is then made possible using complementary numerical simulations.

This paper reports the adaptation of charge pumping on a single DRAM cell for the in situ characterization of individual interface traps. The spatial trap distribution along the different interfaces of the DRAM cell transistor (under the gate and along the ONO/Si lateral interface) has been extensively investigated. Combining charge pumping measurements with numerical simulations allows to extract the exact trap locations.