The intrinsic properties of a CoWP electroless barrier, based on a Pd-free activation process, were evaluated for two different integration schemes, i.e. as a stand alone process, or inside a hybrid stack. The hybrid approach that consists in capping the electroless barrier with a standard SiCN dielectric liner was shown to provide the best compromise in terms of barrier efficiency against Cu diffusion when an oxygen plasma is processed prior the low-K deposition. The process, implemented in a 65 nm technology interconnect stack, evidenced the best electrical and reliable performance for an ultra-thin CoWP barrier, without modifying the dielectric etch stop liner thickness. A thinner SiCN layer, with 20 nm thick CoWP, shows promising results in terms of capacitance improvement. Further process optimization is required for this stack to achieve comparable electrical results.

Atomic deposition control of copper barrier films is becoming a prerequisite in sub 100 nm devices due to inherent performance advantages over conventional deposition techniques like PVD. Therefore Atomic Layer Deposition was used to deposit thin TaN barrier films in 90 urn node dual damascene SiOC structures. The parametrical test results were compared to a state-of-the-art PVD technology and show improved line resistance and via resistance behaviour due to the reduced barrier thickness on side wall and via bottom. In addition, a drastically improved CMP erosion/dishing behaviour was observed due to a reduction in CMP time. The extendibility and scalability of dual damascene metallization upon using Atomic Layer Deposition was shown to be feasible for future process nodes with smaller dimensions.

In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi/sub 2/ shows a "Schottky behavior". Thus we show that nickel allow MOS transistor scaling for future technology.