In this letter, the Schottky-barrier height (SBH) lowering in Pt silicide/n-Si junctions and its implications to Schottky-barrier source/drain p-field-effect transistors (p-SBFETs) are studied experimentally and numerically. We demonstrate that the increase of the n-Si substrate doping is responsible for a larger hole SBH lowering through an image-force mechanism, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations show that the channel doping concentration is also critical for short-channel p/n-silicon-on-insulator SBFET performance

In this paper, the authors study experimentally and numerically the Schottky barrier height (SBH) lowering of Pt silicide/n-Si diodes and its implications to Schottky-barrier (SB) source/drain p-FETs. The authors demonstrate that hole SBH can be lowered through an image-force mechanism by increasing the n-Si substrate doping, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations show that the channel doping concentration is also critical for short-channel n- & p-SOI SBFETs performance

Reactive diffusion of the Ni/Si system has been studied by annealing nickel thin film on (100) silicon crystal. The measurement of the NiSi sheet resistance as a function of the annealing temperature and the type of annealing (Rapid Thermal Annealing and spike one) has been investigated. A kinetic model based on multiphase diffusion has been developed that fits experimental sheet resistance data. Residual stress in the thin film, measured by a curvature measurement technique, is correlated with the nature of the phases in the film. Finally the viscoplastic mechanical behavior of the Ni2Si and NiSi phases is analyzed in the case of low and fast thermal ramps.

This paper presents a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492muA/mum at Ioff: 25nA/mum @ Vdd -1.2V) despite the relatively thick gate oxide thickness used. The inverters' functionality of the FDSOI SRAM cell with a size of 0.99mum2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-V T applications) have been achieved (17ps at V DD =1.1V and 20pA/mum I off ), meeting the ITRS 45nm node requirement for low power CMOS

Combined x-ray diffraction and wafer curvature measurements during annealing of Ni thin films (13 nm) deposited on Si (001) reveal distinct stages in stress development and silicide growth. Thanks to this unique experimental setup, a clear correlation is established between force extrema at distinct temperatures and the appearance of new silicides. It is shown that the transient formation of Ni3Si2 has a strong influence on the overall stress development.

In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications

In this work, a complete low temperature 65 nm process flow using a low-cost, conventional CMOS approach has been investigated. A significant global thermal budget reduction has been achieved (below 500/spl deg/C), especially for the spacer, silicide-protection and salicide modules. The introduction of new materials induced a great transistor performance enhancement in both the digital and analog/mixed-signal domains. The I/sub off/-I/sub on/ figure of merit has been improved by 20%, whereas the matching factors were reduced for both NMOS and PMOS transistors. This new optimized process flow satisfies the strict criteria of transistor reliability.

We propose a new approach to follow stress development during solid state reaction between a Ni thin film and Si (001). Substrate curvature measurements were performed simultaneously with X-ray diffraction at LURE synchrotron radiation facility. The measured curvature yields the average force whereas X-ray diffraction yields the different phases that form as well as the strain variation undergone by these phases. During annealing with a constant heating rate of 2°C/min, Ni grain growth is first observed, followed by the formation of Ni2Si, Ni3Si2 and then NiSi. The Ni2Si formation is correlated with a rapid increase in compressive force. At the end of Ni consumption, the force evolves in tension until NiSi formation, which is accompanied by an additional increase in compressive force and then a final force relaxation at higher temperature. It is interesting to note that the NiSi phase appears at the expense of Ni3Si2, and surprisingly, at the benefit of Ni2Si until the Ni3Si2 is completely consumed. Strain buildup during Ni2Si and Ni3Si2 formation exhibit clear differences. Both Ni3Si2 and Ni2Si phases exhibit a bell shape behavior of the strain evolution versus temperature at variance with predictions from the Zhang and d’Heurle model [Thin Solid Films. 213, 1992, 34].

A wide workfunction (/spl Phi//sub m/) tuning range from 4.29eV to 4.99eV using total silicidation of doped polysilicon gate with nickel is presented. As, B and P but also N, Ge, Sb, In and co-implants, have been investigated to modulate the NiSi gate workfunction by dopant pile up effect at the silicide/dielectric interface. For the first time, defectivity data on dual gate oxide are presented, in correlation with the activation annealing impact and back end of line (BEOL) thermal stress effects as well as thorough TEM observations.

Characterization, modelling and monitoring of interconnect capacitance are of first interest for CMOS and BiCMOS technology development, especially for circuit delay evaluation. An improvement of the Single Pattern Driver method is proposed in this paper to take into account MOST intrinsic and diode leakages which can introduce errors of the order of few hundred aF in advanced nanometer technologies. The accuracy is hugely improved and reaches now 10aF.

Understanding and quantifying stress buildup during silicide formation from metal–silicon reaction is crucial for a proper modeling of stress fields in active areas. In this work we have performed in situ wafer curvature measurements and ex situ X-ray diffraction during the reaction of a Ni thin film with Si(0 0 1). Wafer curvature exhibits marked extrema at temperatures depending on the heating rate. Such behavior is indicative of kinetically limited processes. Isothermal annealings at 230 °C show features similar to those found in ramp heating. Ex situ X-ray diffraction on cooled down samples reveal that the changes in F/w are correlated with the phase formation sequence Ni2Si, Ni3Si2 and NiSi. The F/w trends are explained on the basis of the volume expansion undergone by the different phases during reactions.

Nickel silicide formation and its thermal stability were studied using a stacked hotplate-based low temperature annealing system in the temperature range of 200similar to550degreesC under 1 ami N-2. The effect of TiN capping and two-step annealing on both sheet resistance and surface roughness of silicide films was also investigated. Formation of desirable stoichiometric NiSi was observed by sheet resistance measurement and Xray diffraction over the wide temperature range of 350similar to550degreesC. Phase change from Ni2Si to NiSi was observed around 300similar to350degreesC. Agglomeration of nickel silicide films was observed near 700degreesC while forming the NiSi2 phase. First-step annealing at low temperature (<250degreesC) did not show any effect on NiSi formation in subsequent annealing at higher temperatures. TiN capping was effective in maintaining surface roughness. NiSi was able to handle thermal stress for three hours at 450degreesC without deteriorating the integrity of the film. Uniform and repeatable NiSi formation was achieved by single step annealing.

In this paper, we evaluate the potential of two concepts aiming at the vertical and horizontal reengineering of the S/D junctions of sub-50 nm-CMOS transistors: slim S/D spacers and Ni silicide. We demonstrate the benefit of the lateral spacer size reduction in terms of device performance. For the junction silicidation with Ni, we find electrically equivalent results while the silicidation depth is reduced by 50% with respect to the Co reference. This will enable the use of shallower S/D junctions giving a maximum DIBL and SCE control - an approach, which is especially interesting in combination with slim spacers.

In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basic lattice planes with vertical orientation are often observed inside the grains. NiSi-based CMOS transistors show the same performance as CoSi2-transistors, but nickel can also silicide very narrow poly lines whereas cobalt can not. Moreover, NiSi reduces the STI diode-leakage perimeter, but increases channel side leakage, where CoSi/sub 2/ shows a "Schottky behavior". Thus we show that nickel allow MOS transistor scaling for future technology.

Arsenic implanted into silicon at 2keV to a dose of 1x10(15) cm(-2) is annealed over a wide range of temperature (from 700 to 1100degreesC) and time (from spike to 240sec) in a nitrogen ambient in order to investigate the various thermally-activated phenomena: Activation, Diffusion and Out-diffusion. Xray Fluorescence (XRF), Sheet resistance (Rs) measurements and TCAD simulation have been used to determine the trade-off between activation and dose loss by out-diffusion. It is shown that above a threshold temperature, there is a dramatic increase in the dose loss. For the implant conditions we used, this threshold temperature is found to be about 950degreesC.

In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.