Weighted norm inequalities for the Volterra integral operator with the kernel are characterized in the amalgam space for certain ranges of indices.

A new characterization for the Hardy inequality for the sum of two Hardy-type integral operators is obtained between suitable weighted Lebesgue spaces, for certain ranges of indices.

Boundedness of the sum of two Hardy-type operators with not necessarily nonnegative coefficients has been discussed between amalgams ℓ q (Xu)ℓ b (L r , v) for the case 1 < r, q, b < ∞ where Xu is weighted Banach function space.

Hardy inequalities for the Hardy-type operators are characterized in the amalgam space which involves Banach function space and sequence space.

Necessary and sufficient conditions are given for the validity of discrete Hardy's inequality for the sum of two discrete Hardy-type operators with not necessary non-negative coefficients.

Hardy-inequality has been characterized for sum of two integral operators in weighted Banach function space.

Necessary and sufficient conditions are given for a weighted norm inequality for the sum of two-dimensional Hardy-type integral operators with not necessarily non-negative coefficients.

Boundedness of the Hardy operator (Tf)(x) = f(-infinity)(x)f(t)dt between amalgam spaces l(q)(X(u)) and l((q) over bar)(L(v)((p) over bar)) is obtained, where X(u) is a weighted Banach function space. The adjoint opertor (T*f) (x) = f(x)(infinity)(t)dt has also been treated.

Weighted Hardy-type inequalities between suitable amalgams l(q)(L-p ,u) and l(<(q)overbar>)(L-<(p)overbar> ,v) are characterized. The Hardy-type operator involved in the inequalities involves functions which are not necessarily non-negative.

We present a model for estimating the power consumption of SDRAM at an architectural level. The approach is based on identifying the various operating states for a typical SDRAM, and using the knowledge of current drawn by the memory chip, and fraction of the time spent in each state to estimate the total energy consumption. This model is integrated into Wattch, a simulator for architectural power analysis, and the impact of memory on system energy consumption is analyzed for various programs in the SPEC95 CPU Benchmark suite and some media benchmarks. We further apply this model to study the energy-performance trade-off in designing memory hierarchies. In this paper we discuss the important aspects of our memory power model, and present the results of applying the model to memory hierarchy design space exploration.