A numerically-controlled oscillator (NCO) based upon the COordinate Rotational DIgital Computer (CORDIC) algorithm offers less hardware than the direct form digital NCO at the expense of a second clock that may be as much as N/2 times the nyquist frequency of the system, where N is the number of bits in the NCO output. The CORDIC NCO also uses less hardware than the popular look-up table (LUT) based NCO. Both the LUT NCO and the CORDIC NCO require the additional clock, but the CORDIC clock is easier to synchronize than the LUT NCO clock.

Savings ranging from 36% to 53% in FPGA resources are achieved through a filter design program that simultaneously applies optimum scaling, careful selection of filter order and use of fixed-coefficient multipliers designed with CSD and/or DM techniques. The output of the program is a VHDL description of the optimized hardware that is suitable as input to the Synplify Pro computer program that generates highly optimized FPGA circuits for Xilinx and other FPGA's

CORDIC (Coordinate Rotation Digital Computer) is an iterative digital algorithm, which allows rapid rotation of coordinates in the digital plane. The CORDIC can be used for the calculation of trigonometric functions. This iterative method of performing the transformations uses only shifts and adds. Significant savings in hardware can be achieved through the implementation of the heterodyne circuits of modulators, demodulators and filters using the CORDIC algorithm. In particular, significant hardware savings can be achieved in the implementation of a digital heterodyne filter in VLSI using the CORDIC algorithm.