The effects of three types of program (PGM) disturbance, which are X, XY, and Y mode, on the chip level erase (ERS) threshold voltage (VT) distribution in three-dimensional (3D) NAND Flash memory were studied. A simple model was constructed to emulate both the chip operation and PGM characteristics. It was found that the right tail and peak of ERS VT distribution after PGM operation of a physical block are determined by Y mode and other two modes respectively. We concluded that the difference in channel (CH) boosting level between Y mode and other two modes should be achieved less than a width of initial ERS VT distribution in order not to degrade its right tail. The optimal PGM operation conditions for high CH boosting level were proposed to minimize the band-to-band tunneling (BTBT) current in the dummy WL region.

Program disturbance characteristics of 3D vertical NAND Flash cell array architecture have been investigated intensively. A new 'program Y disturbance' mode peculiar to 3D NAND Flash cell is defined. Swing characteristics of poly-Si channel and increased NOP (number of program) stress have been compared with 2D planar NAND Flash cell. In this paper, new program method pertinent to 3D NAND Flash memory was proposed to obtain program disturbance characteristics for MLC.

MT reliability of MANOS cell was examined from cell array. Lots of retention tail bits occurred even at RT. The fail cells were classified as the manner of q-loss. Defective cell lost abundant charge at early stage, while the q-loss rate of worse cell was faster and lasted in a certain period. Si-cluster in our nitride was supposed to make the worse cell, and this cell redeemed its retention capability by reducing shallow trap in Si-rich nitride.