Проведена отработка методики расчетно-экспериментального восстановления параметров паразитной тиристорной структуры технологического процесса SiGe БиКМОП 0,42 мкм, предназначенной для использования в системах схемно-топологического проектирования.

The volt-ampere characteristics (VAC) at temperatures from minus 197 ° C to 30 ° C of n-JFET and p- JFET, manufactured at JSC "SPE "Pulsar" using a complementary bipolar technological route, are considered. Features of the VACs are described and the obtained temperature approximations of the main parameters are given. We have compared the JFET's VACs manufactured at JSC "SPE "Pulsar" and JSC "Integral".

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the "freezing out" of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range Delta T = 150-330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range Delta T = 150-77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

Рассматриваются два варианта построения интегральных ОУ: 1) промышленных ОУ типа LM124, не уязвимых к воздействию ТЗЧ; 2) быстродействующих ОУ с улучшенными точностными и скоростными характеристиками. В обоих случаях используется синергетический подход, основанный на введении в структуру аналога элемента с режимом обострения. Two options for the construction of integrated op-amps are considered: 1) industrial op-amps of the LM124 type, which are invulnerable to the effects of HCP; 2) high-speed op-amps with improved accuracy and speed characteristics. In both cases, a synergistic approach is used, based on the introduction of an element with an aggravation mode into the structure of the analogue.

Lateral instability is inherent in power transistors structures, consisting of several simple transistors connected in parallel. The large number of transistor elements complicates the analysis of such instability. The introduction of suppressing resistors makes it possible to prevent the occurrence of lateral oscillations, however there are no unambiguous criteria for achieving stability this way. The matter is further complicated by the fact that transistor exhibits nonlinear operation in a typical amplifier stage, and the operating conditions in many cases correspond to a relatively wide range of frequencies. In this paper, we present an analysis of lateral instability of a power amplifier stage, created on a basis of modern GaN field-effect transistor (FET). We had designed all dies and circuits for this FET. The main feature of the analysis is that we carried it out in the time domain, which made possible to estimate the stability of the stage not only under the excitation power pulse, but also after the end of the pulse. Our approach makes it possible to assess the stability of the amplifier between the excitation pulses, which is very important from the operational point of view. We calculated the estimates of operational stability and stability factor using a simplified transistor model, with the multi-element model reduced to a two-element model. Nevertheless, the results of the estimates retain their significance in real conditions, when the introduction of suppressing resistors creates a significant margin of stability, including the actual operating frequency band of the stage. To date, the data we have obtained after the manufacture of the samples only partially confirms the calculated estimates, due to the complexity of managing the experimental studies. However, there are no recorded results, which deny our estimates for the model.

Проведены эллипсометрические исследования изменений свойств приповерхностных слоёвGaAs-гетероструктур, которые подвергались последовательно трём обработкам: в кислородной плазме, в растворе соляной кислоты и термическому отжигу.Показано, что достаточно простая процедура эллипсометрических измерений позволяет следить за состоянием поверхности гетероструктур

Представлены конструкции и технология изготовления конструктивных теплоотводящих элементов в изделиях силовой электроники. Рассмотрены способы металлизации коммутационных плат силовых модулей, обеспечивающие минимальное электрическое сопротивление силовых цепей и высокую адгезию металлизации к поверхности платы

АО «ГЗ «Пульсар», 105187, Москва, Окружной проезд, д. 27 Первая часть статьи посвящена вопросам зарождения и развития умножителей частоты с момента появления первых работ в области генерации радиотехнических сигналов для осуществления передачи информации

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

A unified SPICE macromodel of the SiGe HBTs taking into account radiation effects is presented. It consists of two parts: 1) the standard core model (GP, VBIC, HICUM, MEXTRAM) selected by the designer; 2) an additional subcircuit taking into account the radiation-induced current and voltage shifts. The macromodel was included on SPICE-like simulators. The advantages of SPICE-RAD version of HBT model are: 1) high accuracy of description for device characteristics; 2) convenience to use for IC designers; 3) simplicity of parameter determination. The I-V characteristics of SiGe HBTs irradiated by gamma-rays, protons, neutrons, electrons are measured and simulated. The error for static characteristics is 10–15% and for dynamic characteristics is 15–20% in wide range of doses and/or fluencies.

In this paper the manufacturing process for AlN-ceramic heat-sink plates, using metallization com-pound based on refractory metals is presented.Main applications are power transistor cases, power modules, passive elements created with high-temperature soldering.AlN-ceramic cases could serve as an alternative to the BeO-ceramics cases of power semiconductor devices.

Представлена конструкция герметичного металлокерамического корпуса типа ТО-254, являющегося аналогом металлостеклянного корпуса

In article interrelation of the linear operation range of a CMOS differential difference operational amplifier (DDOA) with the main parameter of the pass characteristics of its input differential stages (DS), the limiting voltage (V lim ), is considered. The results of mathematical and comparative computer modeling of the dependence of V lim typical CMOS DS on the channel width of transistors at different static currents for three CMOS technological foundry processes (0.25 um SiGe CMOS, 0.35um SiGe CMOS and 0.6 um Si CMOS) are presented. Recommendations are given for increasing the maximum slew rate of the output voltage (SR) of the DDOA, which are based on the introduction into each input DS of a differentiating circuit of transient correction.

ОСНОВНЫЕ ПОДХОДЫ К РАЗРАБОТКЕ МОДЕЛЕЙ АНАЛОГОВОЙИ СВЧ ЭЛЕКТРОННОЙ КОМПОНЕНТНОЙ БАЗЫ ДЛЯ ИСПОЛЬЗОВАНИЯ В САПР Е.М

The parameter optimization features of CMOS operational amplifiers (OA) based on dual-input-stage under constraints on power consumption, unity gain frequency, phase margin, open loop gain and compensation capacitance are considered. It is shown that the maximum slew rate of the output voltage is proportional to the DC currents of dual-input-stage due to the usage of current mirror based push-pull parallel channels. The recommendations to design of high-speed CMOS OA with wide range of dynamic characteristics are given.

The article proposes a method of bandwidth extension of the analog integrated circuit of the variable-gain amplifier (VGA) based on SiGe BiCMOS technology with the rules of 0.18 µm. The designed VGA has a linear (in dB) control characteristic. The authors consider the VGA architecture and present its design outputs. They describe the properties of two modifications of the VGA integrated circuit – with classical correction of the response and with the circuit of the parasitic capacitance cancellation in the high-impedance node. The article shows that the second circuit solution allows increasing the upper frequency limit of the VGA by a factor of 1.8-2.

ФГБОУВО «Московский технологический университет» (МИРЭА), 119454, г.Москва, пр-т Вернадского, 78 3 Донской государственный технический университет (ДГТУ), 344000, г.Ростов-на-Дону, пл.Гагарина, 1 В статье приводится краткий анализ основных параметров и типов драйверов сверхскоростных аналого-цифровых преобразователей (АЦП).Приводится информация о характеристиках серийных АЦП с частотой преобразования до 5,4 ГГц.Рассмотрены основные схемы включения широкополосных усилителей (ШПУ) в качестве драйвера дифференциальных АЦП.Представлены результаты измерений малосигнальных и нелинейных характеристик, а также дана расчётная оценка быстродействия АЦП с

The article proposes a method of bandwidth extension of the analog integrated circuit of the variable-gain amplifier (VGA) based on SiGe BiCMOS technology with the rules of 0.18 µm. The designed VGA has a linear (in dB) control characteristic. The authors consider the VGA architecture and present its design outputs. They describe the properties of two modifications of the VGA integrated circuit – with classical correction of the response and with the circuit of the parasitic capacitance cancellation in the high-impedance node. The article shows that the second circuit solution allows increasing the upper frequency limit of the VGA by a factor of 1.8-2.