D & TOF-SIMS instruments are used in conjunction with other analytical techniques in order to identify the sources of metallic contamination and particle-type defects. In this paper D & ToF-SIMS are used to identify metals in the P-type buried layer of BiCMOS transistors and eliminate them in order to improve the overall device performance and process yield. Copyright (C) 2010 John Wiley & Sons, Ltd.

We present a comprehensive investigation of temperature dependence of breakdown voltage, DC current gain (β), and Early voltage (VA) for complementary SiGe-npn and SiGe-pnp bipolar transistors fabricated on an advanced CBiCMOS technology on thick-film SOI. Both SiGe-npn and SiGe-pnp transistors show decreasing VA as ambient operating temperature increases from −60°C to +200°C for low collector current densities (JC ≤ 5.0 µA/µm2) with a near linear inverse temperature (1/T) relationship. We also demonstrate in the region historically defined by weak self-heating interactions that VA maintains minimal sensitivity to operating temperature.

A production released complementary-SiGe BiCMOS technology on SOI has been developed for high speed analog and RFIC applications. It features matched SiGe:C PNP and NPN transistors. The PNP shows cutting edge performance metrics with β·VA =17,000 and near record fT·BVCEO ≥ 195GHz·V for a 5V process while demonstrating best in class linearity on a fully differential amplifier design. A modular process flow was leveraged to enhance the Analog design needs for the platform. For higher-speed lower power, we also demonstrate a low voltage SiGe NPN with peak fT of 50 GHz at low-bias (VCE = 0.5V), ideal for load line drive. Finally, we discuss core CMOS devices which utilize a dual-gate oxide process for improved mixed-signal mixed-voltage design and better optimization of digital blocks.

This work details the investigation of potential problems in Complimentary BiCMOS technology, especially PNP transistors arrays. Optical examination of the wafer revealed defects in the P Buried Layer (PBL) areas of the die. Electrical testing correlated these PBL defects to PNP array current leakage. As the PBL module is completed very early on in the process, we devised a shortloop (SL) to reproduce these defects and identify the root cause of current leakage.

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f T and noise figure improves slightly with footprint, and peak f MAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.