In this work, a 2 Stack cascode Power Amplifier (PA), for 5G applications at 28GHz has been designed and fabricated with 22nm FDX technology from GlobalFoundries. An enhanced device variant of Super Low Voltage Threshold (SLVT) called ENBFMOAT is used. The architecture of PA is based on pseudo differential 2 stack cascode with on chip input and output baluns. A new layout design style has been improved to mitigate the phase delays. Moreover, connecting the Nwell to front gate to strength the ground plane. A sandwiched output balun style is utilized to increase the coupling and reduce the loss. All these improvements provided us with 19dBm linear output power (P sat ) and peak Power Added efficiency (PAE) of 49%. The reliability for 10 years is also investigated and ensured the long life PA working time efficiently. To best authors knowledge, the presented PA introduced the highest PAE combined with P sat in CMOS/SOI technology.

In this paper, we present the latest 22FDX Ⓡ 5G power amplifier (PA) performance enhancement based on a new PA device, EDMOS. A 2-stage PA measured at 22. 9dBm Pout and 33% peak PAE with EDMOS as core device at PA stage. EDMOS achieves 20% higher voltage handling than the popular reference SLVT devices used in 22FDX Ⓡ 5G PA design [1], while not sacrificing the device on-resistance ($\mathrm{R}_{\mathrm{O}\mathrm{N}}$). The cut-off frequency ($\mathrm{f}_{\mathrm{T}}$) and maximum oscillation frequency ($\mathrm{f}_{\mathrm{M}\mathrm{A}\mathrm{X}}$) are 281 GHz and 389 GHz, respectively, which is suitable for 5G PA applications. For Common-Source ($\mathrm{C}_{\mathrm{S}}$) device, EVM measurement is also showing $\sim$25% improvement over the reference SLVT device. The Pout and PAE of 2-stage PA are achieving a new record in the 22FDX Ⓡ CMOS based PA design, which makes this device as a strong candidate for 5GmmW (millimeter wave) PA in handset as well customer premises equipment (CPE).

New extended drain field effect transistors, EDNFET and EDPWNFET, with technology and layout optimization for mmW PA on 22FDX technology is carefully carried out in this work. Optimization through work-function engineering, gate resistance routing at PA array, and drain extension through multiple contact to poly pitch (CPP) results in 20% reliability enhancement while not sacrifice on-resistance (Ron). 2 Stage PA consist of optimized device as output stage shows a 2x improvement in output power (Pout) reaching 23dBm as well as 3% PAE enhancement at 28Ghz. To our knowledge, this is the best result we see on the 22FDX ® technology at 28Ghz

A 22nm FD-SOI Power Amplifier (PA) for 5G communication at 28 GHz is demonstrated. A dual-stage approach together with stacking techniques and optimized transistor-interconnection layout is used to achieve a measured peak PAE above 31% with an output power of 21.0 dBm. Besides output power and PAE, the PA demonstrated 12.5 dBm at −28 dB EVM with 64-QAM CF -OFDM 5G modulated signal and 18.5 dBm with DFT-s-OFDM QPSK modulated signal at −19 dB ACLR with 100-MHz bandwidth with a linear PAE of 20%. To the best of the authors knowledge, the presented PA shows the highest linear power and efficiency with QPSK while its 64-QAM modulated output power outperforms by 1 dB the state of the art while also reducing the EVM by 1 dB, when compared against 2-stage PA silicon implementations. Finally, an output-power degradation below 0.05 dB after 66 hours of stress at 21 dBm power level has been shown to demonstrate excellent reliability.

Although technology scaling to deep submicron enable higher degrees of semiconductor integration, highly integrated circuit have become increasingly sensitive to the slightest parameter drift. One of the main causes of parameter degradation in recent technologies is the Hot Carrier Injection (HCI), a progressive wear out phenomenon whose understanding and modeling has become mandatory in new CMOS nodes. Therefore, we present in this paper a new HCI reliability model for Fully Depleted Silicon On Insulator (FDSOI) MOSFETs which covers the RF/mmWave (Radiofrequency /millimeter wave) applications taking into account back bias operation.

A unique NFET device with specially treated region underneath the buried-oxide (BOX) in the state-of-the-art 22 nm FD-SOI technology (GLOBALFOUNDRIES’ 22FDX ® technology), displays excellent switch performance for wide frequency range. Very gradual frequency response of the switch insertion-loss (IL) makes the device ideal choice for 80 GHz applications with sub-2 dB IL. Other RF figure of merits (FoMs) like cut-off frequency fT (351 GHz) and maximum oscillation frequency fMAX (317 GHz) along with the DC FoMs indicate that the device can be utilized for the power-amplifier (PA) and low-noise amplifier (LNA) applications also. For mmWave switch circuit designs, accurate modelling is important to predict the switch behaviour for wide frequency range. This paper proposes the modelling methodology to predict the unconventional frequency response of switch IL accurately up to 80 GHz.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The fMAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

This work shows the excellent HCI (hot-carrier injection) reliability that 22FDX demonstrates for mmWave PA applications. The underlying device physics to explain this performance are also shown. Due to the fact that fully depleted SOI (FDSOI) eliminates the lateral bipolar device, the MOSFETs in 22FDX ® technology have an increased BVDSs when compared to a device in a partially depleted SOI (PDSOI) technology. A 2-stack PA is presented that demonstrates excellent reliability against all HCI stress. The device aging model is built based on the device stress data specific for PA applications. RelXpert is used to simulate device aging based on the model and suggests excellent PA reliability even under the worst mismatch condition.

This paper reports the high frequency (HF) noise characterized performance and modeling on 22nm FD-SOI technology transistor (GLOBALFOUNDRIES’ 22FDX ® technology) from 2 GHz to the maximum E-band millimetre-Wave (mmWave) frequency of 90 GHz. The measurement was performed using the Focus Microwaves noise system with different customised setups and optimised for each discrete frequency bands. The data measured from each frequency bands were subsequently combined to produce the noise spectrum covering from 2 GHz to 90 GHz, with high accuracy, good continuity and excellent correlation to the compact model. The 22FDX ® technology transistor demonstrated very low mmWave noise figure, which is favourable for RF and mmWave applications such as LNA.

This paper addresses the impact of back-gate biasing to DC, RF/millimeter-Wave (mmWave) and high frequency (HF) noise in 22nm FD-SOI technology (GLOBALFOUNDRIES’ 22FDX® technology). The front-gate and the back-gate cut-off frequency fT, together with the maximum oscillation frequency fMAX, were extracted from the four-port S-parameters data. The maximum achieved front-gate/back-gate fT and fMAX for the NFET is 350/85 GHz and 370/23 GHz respectively. In addition, 22FDX® technology demonstrated a tuneable HF noise parameter by using the back-gate biasing to achieve best-in-class low noise level. Two front-end (FE) modules were presented, which exploit the unique feature of back-gate. This unique feature allows superior designs with excellent combination of performance, power consumption and development cost, for emerging applications such as IoT, Telecommunication UE, RF and mmWave circuits with high speed connectivity and networking.

In this work, the thermal coupling resistance (R12) between the reference transistor and the output transistor in a current mirror is characterized by two different measurement techniques: the constant voltage, and the constant current R12 extractions. The extracted R12 from both methods are very similar. The constant voltage method is deemed to be more physical or accurate than the constant current method. Further TCAD simulation agrees well with R12 measurement data.

The electrical and thermal performance scaling from transistor to array was studied in this paper to help improve the predictive modeling of the electrical-thermal behavior of bipolar arrays. The dc and ac performance scales well at low bias but not to the medium and high bias because thermal resistance does not scale to the total emitter area. It is demonstrated that after the correction of the RTH in array models, the simulation can predict the electrical-thermal behavior of power arrays.

This paper gives a brief overview on recent advances in bipolar junction transistor (BJT) modeling and related simulation applications in circuit design. This work starts with a review of existing BJT compact model formulations, and covers a broad range of advanced topics such as precision temperature modeling, sub-circuit design, mismatch and corner modeling, and BJT scalable model.

The RF safe-operating-area of a variety of both bulk and thick-film SOI SiGe HBTs SiGe has been investigated using DC and pulsed-mode output characteristics, as well as RF gain and linearity measurements. SOI SiGe HBTs are found to suffer more from self-heating than bulk devices under DC operating conditions, as expected, due to their naturally higher thermal resistance. However, in terms of RF performance, operation of SiGe HBTs on SOI beyond the traditionally-defined safe-operating-area showed only minor degradation in RF metrics, and improved RF linearity. High-injection phenomena are suggested as possible explanations for the observed suppression of self-heating-induced degradation and thermal runaway in these SiGe HBTs on SOI operating under RF operating conditions.

Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint area increase. Peak f T and noise figure improves slightly with footprint, and peak f MAX improves slightly then decreases significantly at very large footprint area. A generic tube-area-limited thermal resistance model for BiCMOS devices on SOI is also proposed.

A new piecewise-polynomial interface method (PIM) for discretizing elliptic problems with complex interfaces between high-contrast materials is derived, analyzed and tested. A Krylov-accelerated interface multigrid approach (IMG) solves the discretization efficiently. Stability and convergence are proved in one dimension, while an extensive array of numerical experiments with complex interfaces and large coefficient transitions demonstrate the accuracy, efficiency and robustness of the method in two dimensions.

A unified electro-thermal safe operating area (SOA) expression is proposed in this paper to evaluate self heating, impact ionization, and hot carrier (HC) degradation effects simultaneously in a full range of bipolar transistor operation. This SOA is demonstrated by experiments for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) by extracting principle parameters from discrete transistors and current mirrors. Also, time dependent reliability tests have been fulfilled for several meaningful bias points within this SOA at the fixed V BE and V CE . Avalanche induced HC injection was another important factor to restrict device performance. Finally, the modified electro-thermal SOA by HC reliability is suggested here.

A unified electro-thermal safeoperating area(SOA)expression isproposed inthis papertoevaluate selfheating, impactionization, andHot Carrier (HC) degradation effects simultaneously inafull rangeofbipolar transistor operation. ThisSOA isdemonstrated by experiments fora SiGehetero-junction bipolar transistor (HBT)fabricated onsilicon oninsulator (SOI)byextracting principle parameters fromdiscrete transistors andcurrent mirrors. Also,timedependent reliability tests havebeen fulfilled forseveral meaningful biaspoints within this SOA atthefixed VBEandVCE.Avalanche induced HC injection wasanother important factor torestrict device performance. Finally, themodified electro-thermal SOA byHC reliability issuggested here. IndexTerms- SiGeHBT,safeoperating area,self heating, impact ionization, hotcarrier reliability. 2.0 1.8 1.6- 1.4- E 1.2 ;1.0- E A0.8- 0.6- 0.4- 0.2 0.0

X-ray total ionizing dose effects in both fully-depleted and partially-depleted SiGe HBT-on-SOI transistors are investigated at room and at cryogenic temperatures for the first time. Devices irradiated in grounded and forward-active mode configurations exhibit a different behavior depending on the collector doping of the device. The degradation produced by 10 keV x-rays is compared to previously reported 63 MeV proton results on the same fully-depleted SiGe HBT-on-SOI devices, showing decreased degradation for proton irradiation. Both collector and substrate bias are shown to affect the two-dimensional nature of the current flow in these devices, resulting in significant differences in the avalanche multiplication characteristics (hence, breakdown voltage) across temperature.

The thermodynamic stability of device-relevant epitaxial SiGe strained layers under proton irradiation is investigated using X-ray diffraction techniques, and compared with its stability constrain under high-temperature annealing. Irradiation with 63MeV protons is found to introduce no significant microdefects into the SiGe thin films, regardless of starting stability condition of the SiGe film, and thus does not appear to be an issue for the use of SiGe HBT technology in emerging space systems. The strain relaxation of SiGe thin film under thermal annealing, however, is sensitive to the composition and thickness of the as-grown samples, as expected, with the subsequent lattice relaxation of the unstable samples occurring at a much higher rate than that of metastable samples.