Over the last decade SEMATECH has provided significant guidance in predicting mask costs and their potential effects on the cost of manufacturing semiconductors. Additionally, these projections have been used to appropriately fund activities that could have the most impact on reducing mask costs, improving quality and cycle time. The most recent cost projections provide a comprehensive look at the impact of improvements to the mask fabrication process. We will provide projections that clearly indicate that appropriately funded mask technologies can have a significant impact on manufacturing yields and hence, cost and cycle time.While historical mask cost projections were realistic, the new projections represent the best estimates for mask costs over the next several years based on the current mask technology and processes'. These projections are significantly more optimistic than previous estimates. These changes are due primarily to the introduction of new mask repair technologies, improvements in focused ion beam (FIB), nano-machining and femto-second laser repair.

in many semiconductor markets, the largest fraction of total lithography cost is photomask cost; therefore any improvements in that area can have a noticeable impact on net chip cost. A significant yield loss mechanism for advanced photomasks is through nonrepairable defects. Providing improved methods to repair defects allows for improvements in mask yield and, therefore, the cost to make a defect-free mask and eventually the cost to produce the integrated circuit. However, the connection between mask yield and integrated circuit price is not a first-order relationship because it bridges between the mask supplier and end-user. SEMATECH and other worldwide consortia have, in the past, bridged this gap by sponsoring programs to develop improved mask infrastructure tools. A significant investment has been made in mask repair tool technology, but the quantitative benefit and return on investment has not been summarized until now. This paper attempts to show the strong benefits to the photomask and semiconductor industries from improving mask repair.

To enable patterning of 65‐nm half pitch and smaller dimensions, optical projection lithography is being extended with 193‐nm wavelength using water immersion lenses. To enable this extension more complex masks and greater comprehension of variations in the lithography process are being integrated into the integrated circuit design process. Metrology will play a critical role in defining these lithography friendly design rules and practices. The effects of line edge and line width roughness are also becoming increasingly apparent in device performance, so metrology tools need to be modified to accurately measure these variations as well. Tools for measuring critical dimensions, including roughness, with high precision and for quantifying pattern fidelity will be critical to enable the extension of lithography to smaller dimensions.

Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the fourth in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey contains all of the 2004 survey questions to provide an ongoing database. Additional questions were added to the survey covering operating cost factors and equipment utilization. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services, operating cost factors and equipment utilization. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from eight major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market. This participation rate is reduced by one captive from 2004. Note: Toppan, DuPont Photomasks Inc and AMTC (new) were consolidated into one input therefore the 2004 and 2005 surveys are basically equivalent.

Polarization dependent diffraction efficiencies in transmission through gratings on specially designed masks with pitch comparable to the wavelength were measured using an angle-resolved scatterometry apparatus with a 193 nm excimer source. Four masks -- two binary, one alternating and one attenuated phase shift mask -- were included in the experimental measurements. The validity of models used in present commercially available simulation packages and additional polarization effects were evaluated against the experimental scattering efficiencies.

In extreme ultraviolet lithography (EUVL), the technology specific requirements on the mask are a direct consequence of the utilization of radiation in the spectral region between 10 and 15 nm. At these wavelengths, all condensed materials are highly absorbing and efficient radiation transport mandates the use of all-reflective optical systems. Reflectivity is achieved with resonant, wavelength-matched multilayer (ML) coatings on all of the optical surfaces -- including the mask. The EUV mask has a unique architecture -- it consists of a substrate with a highly reflective ML coating (the mask blank) that is subsequently over-coated with a patterned absorber layer (the mask). Particulate contamination on the EUVL mask surface, errors in absorber definition and defects in the ML coating all have the potential to print in the lithographic process. While highly developed technologies exist for repair of the absorber layer, no viable strategy for the repair of ML coating defects has been identified. In this paper the state- of-the-art in ML deposition technology, optical inspection of EUVL mask blank defects and candidate absorber patterning approaches are reviewed.

Nanoimprint lithography is a contact-lithogoraphy technology invented in 1996 as a low-cost alternative to photolithography for researchers who need high resolution patterning. Initially perceived as a trailing-edge technology for low-cost device fabrication, it has been recently demonstrated to achieve sub-10 nm resolution and alignment, which equal or surpass even the most advanced photolithography today. At Hewlett-Packard, we have successfully used it to fabricate switchable molecular memory arrays with a dimension of 65 nm half pitch. Nanoimprint has been placed on the International Technology Roadmap for Semiconductors (ITRS) as a candidate for next-generation lithography (NGL) for insertion in the 32 nm node in Y2013. The switch from using light to using contact to pattern will indeed bring new challenges, the most important of which are alignment and the 1x mask/template. For alignment, one imprint tool maker has achieved alignment of +/- 7 nm 3 sigma using Moire patterns. For template fabrication, the lack of OPC and other sub-resolution features produced larce savings in patterning. but it is nearly cancelled out by the need for more aggressive inspection because of the smaller tolerable defect size. The two combined to make the predicted cost of nanoimprint template to be similar to photomasks for 45-nm half pitch. At 32-nm half pitch, EUVL masks do not have complicated sub-resolution features and are predicted to be cheaper than comparable nanoimprint templates provided that the former's defect levels can be reduced to what is required for economical manufacturing. In both cases, the challenges are not insurmountable and solutions are being actively pursued. However, if nanoimprint is indeed the disruptive technology to photolithography, it needs to take its initial aim at the low-end market rather than mount a frontal challenge at semiconductor manufacturing, which is the high-margin customers that photolithography will pursue and protect at all cost. The recent development in nanotechnology will lead to the commercialization of a new class of nanoscale devices requiring a high-resolution lithographic technique that does not have all the functionalities of photolithography. This approach will provide an initial customer base for nanoimprint to develop and improve and position it to challenge photolithography in the distant future.

The extension of optical projection lithography through immersion to patterning features with half pitch ⩽65 nm is placing greater demands on the mask. Strong resolution enhancement techniques (RETs), such as embedded and alternating phase shift masks and complex model-based optical proximity correction, are required to compensate for diffraction and limited depth of focus (DOF). To fabricate these masks, many new or upgraded tools are required to write patterns, measure feature sizes and placement, inspect for defects, review defect printability and repair defects on these masks. Beyond the significant technical challenges, suppliers of mask fabrication equipment face the challenge of being profitable in the small market for mask equipment while encountering significant R&D expenses to bring new generations of mask fabrication equipment to market. The total available market for patterned masks is estimated to be $2.5B to $2.9B per year. The patterned mask market is about 20% of the market size for lithography equipment and materials. The total available market for mask-making equipment is estimated to be about $800M per year. The largest R&D affordability issue arises for the makers of equipment for fabricating masks where total available sales are typically less than ten units per year. SEMATECH has used discounted cash flow models to predict the affordable R&D while maintaining industry accepted internal rates of return. The results have been compared to estimates of the total R&D cost to bring a new generation of mask equipment to market for various types of tools. The analysis revealed that affordability of the required R&D is a significant problem for many suppliers of mask-making equipment. Consortia such as SEMATECH and Selete have played an important role in cost sharing selected mask equipment and material development projects. Governments in the United States, in Europe and in Japan have also helped equipment suppliers with support for R&D. This paper summarizes the challenging business model for mask equipment suppliers and highlight government support for mask equipment and materials development.

Many technological challenges exist for the timely introduction of successive generations of integrated circuits with decreasing feature size. Lithography at dimensions commensurate with those described in the International Roadmap for Semiconductors at technology nodes with half pitch ≤45nm will require complex masks for 193nm immersion or EUV masks. ISMT has a five-year alliance with the State University of New York at Albany to develop EUV mask blanks and EUV resist. A process line to develop low defect extreme ultraviolet (EUV) mask blank multilayers is operational. ISMT is also working with commercial suppliers, who are fabricating EUV mask substrates and multilayer-coated mask blanks. Tools and processes for fabricating, inspecting, reviewing defects and repairing defects for EUV mask blanks are being developed as well. In addition, standards for EUV mask blank requirements and strategies for maintaining defect free EUV masks are being investigated.

Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the third in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey builds upon the 2003 survey to provide an ongoing database using the same questions as a baseline with only a few minor changes or additions. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from ten major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market.

To evaluate the ability to achieve the CD control requirements listed in the International Technology Roadmap for Semiconductors (ITRS) and to set error budget targets for focus, dose, PEB temperature uniformity, and mask CD control, statistical lithography simulation was used. A statistical model of total CD control, including the effects of intrafield and interfield error sources, was developed. The exposure tool settings such as wavelength, NA and partial coherence, focus and dose error budgets, lens aberration levels, mask type and pattern pitch values were determined for each node. Monte Carlo simulation was used to predict the CD error due to intrafield dose and focus errors. The contribution to CD error due to the mask was determined using mask CID control values in the ITRS and a calculated MEEF value at various defocus settings. The contribution to CD error due to PEB temperature variations, across wafer dose variations, and variation of aberrations and flare within the exposure field was also simulated. To meet ITRS CD control targets for 130-nm and 90-nm nodes, an alternating PSM mask is required along with a larger CD printed in resist than indicated in the ITRS. Meeting ITRS CD control requirements for 65-nm node and beyond not possible using assumptions detailed here, even with a near ideal APSM. The simulations predicted that if a relaxed pitch and a larger CD in resist were used at the 32nm node, 193nm immersion lithography in combination with a nearly ideal alternating PSM might provide CD control that is comparable to that obtainable using extreme ultraviolet lithography (EUVL).

Phase Shift Masks (PSM) for Extreme Ultraviolet Lithography (EUVL) have the potential for extending the lithographic capability of EUVL beyond the 32-nm node. The concept of EUV PSM structures can be implemented either by adding absorber structures on top of the Mo/Si multilayers (additive approach) or by partial etching into the multilayers (subtractive approach). Among many technical challenges, evaluating optical constants of absorber materials is the most important issue particularly for PSM by the additive approach (PSM-ADD), while the etch stop capability and the etch selectivity with vertical sidewall profile are the main technical challenges for PSM fabricated by the subtractive method (PSM-SUB). For fast turn around of PSM development, the indirect optical constant evaluation through material analysis is a useful metrology technique. The optical constant of TaSiN extracted from Rutherford Backscattering Spectroscopy (RBS) data agrees well with that obtained from the direct measurement by transmission interferometric technique. For PSM-SUB, the concept of embedding B4C and NiFe etch stop layer (ESL) is verified by measuring reflectivity of the ESL embedded substrates and demonstrating good etch stop capability.

We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NA's increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.

Defect printability and inspection studies were conducted on a programmed EUV defect mask. The mask was fabricated using Ta-based absorber stack on a Mo/Si multilayer coated 6025 plate. The defect pattern contains a variety of types of defects. The defect printing was performed on the Engineering Test Stand (ETS), which is the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The result showed that the printability of defects depended on the defect type and that either notches in or protrusions from absorber lines were the first to print. The minimum printable defect size was approximately 15 nm (1X). Defect inspection was performed on a 257-nm wavelength mask inspection system in die-to-die mode. Seventy-eight out of 120 programmed defects were detected when using 50% detection sensitivity. Maximum detection sensitivity was also tried. However, the number of defects is overwhelmed by the nuisance defects. The minimum defect detected was 52 nm in width. Simulations with a 2-D scalar model are used to verify the results.