Background Schools are high-risk settings for SARS-CoV-2 transmission, but necessary for children's educational and social-emotional wellbeing. Previous research suggests that wastewater monitoring can detect SARS-CoV-2 infections in controlled residential settings with high levels of accuracy. However, its effective accuracy, cost, and feasibility in non-residential community settings is unknown. Methods The objective of this study was to determine the effectiveness and accuracy of community-based passive wastewater and surface (environmental) surveillance to detect SARS-CoV-2 infection in neighborhood schools compared to weekly diagnostic (PCR) testing. We implemented an environmental surveillance system in nine elementary schools with 1700 regularly present staff and students in southern California. The system was validated from November 2020 to March 2021. Findings In 447 data collection days across the nine sites 89 individuals tested positive for COVID-19, and SARS-CoV-2 was detected in 374 surface samples and 133 wastewater samples. Ninety-three percent of identified cases were associated with an environmental sample (95% CI: 88%-98%); 67% were associated with a positive wastewater sample (95% CI: 57%-77%), and 40% were associated with a positive surface sample (95% CI: 29%-52%). The techniques we utilized allowed for near-complete genomic sequencing of wastewater and surface samples. Interpretation Passive environmental surveillance can detect the presence of COVID-19 cases in non-residential community school settings with a high degree of accuracy. Copyright (c) 2023 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

Schools are high-risk settings for SARS-CoV-2 transmission, but necessary for children's educational and social-emotional wellbeing. While wastewater monitoring has been implemented to mitigate outbreak risk in universities and residential settings, its effectiveness in community K-12 sites is unknown. We implemented a wastewater and surface monitoring system to detect SARS-CoV-2 in nine elementary schools in San Diego County. Ninety-three percent of identified cases were associated with either a positive wastewater or surface sample; 67% were associated with a positive wastewater sample, and 40% were associated with a positive surface sample. The techniques we utilized allowed for near-complete genomic sequencing of wastewater and surface samples. Passive environmental surveillance can complement approaches that require individual consent, particularly in communities with limited access and/or high rates of testing hesitancy.

It is currently unknown whether endovascular filament (EF) models of acute subarachnoid hemorrhage (SAH) introduce any ‘side bias’ upon cerebrovascular reactivity by virtue of unilateral carotid manipulation, unilateral EF insertion, or potentially ipsilateral site of intracranial rupture. In this study, three experimental groups of adult male wistar rats were used: non-operated controls (n=20), sham operated controls (n=8), and SAH groups (n=26). All were anaesthetized with intraperitoneal 25% urethane (1 g/kg) except n=2 anaesthetized with intraperitoneal hypnorm/hypnovel. SAH was created by advancing an intraluminal thread through the intracranial internal carotid artery from an extracranial source in the neck. Using in vitro wire myography in all three groups, middle cerebral artery (MCA) responses ipsilateral and contralateral to EF insertion were compared using a range of vasoconstrictors and vasodilators within 3 h of SAH. No significant side differences in MCA reactivity were found with any agent in any group or sub-group analysed. In conclusion, EF-SAH models do not appear to introduce any significant ‘side bias’ upon ipsilateral MCA reactivity by virtue of the potentially confounding combination: (1) unilateral carotid manipulation, (2) unilateral EF insertion or (3) potentially ipsilateral intracranial rupture. They may thus be more confidentally used for post-SAH ex vivo cerebral vessel study—acute or delayed.

As Processing-In-Memory (PIM) hardware matures and starts making its way into normal compute platforms, software has an important role to play in determining what to perform where, and when, on such heterogeneous systems. Taking an emerging class of PIM hardware which provisions a general purpose (RISC-V) processor at each memory bank, this paper takes on this challenging problem by developing a software compilation framework. This framework analyzes several application characteristics - parallelizability, vectorizability, data set sizes, and offload costs - to determine what, whether, when and how to offload computations to the PIM engines. In the process, it also proposes a vector engine extension to the bank-level RISC-V cores. Using several off-the-shelf C/C++ applications, we demonstrate that PIM is not always a panacea, and a framework such as ours is essential in carefully selecting what needs to be performed where, when and how. The choice of hardware platforms - number of memory banks, relative speeds and capabilities of host CPU and PIM cores, can further impact the "to PIM or not" question.

State-of-the-art high-throughput DNA sequencers output terabytes of short reads that typically need to be aligned to a reference genome in order to perform downstream analyses. Because alignment typically dominates the total run time of bioinformatics pipelines, a number of recent work sought to accelerate it in hardware. However, existing FPGA implemen-tations did not fully optimize the alignment algorithms for the FPGA hardware and mainly focused on a subset of alignment problems, e.g., ungapped alignment with a limited number of mismatches, which hinder their practical utility. In this work, we analyze the existing alignment methods and identify and leverage opportunities for FPGA acceleration. Our alignment framework, SALIENT, first carries out an ultra-fast ungapped alignment, which supports a flexible number of mismatches. Based on the underlying bioinformatics pipeline and the information provided by the ungapped aligner, SALIENT then identifies a fraction of reads that need to go through its gapped aligner, thus improving alignment throughput. We extensively evaluate SALIENT using diverse datasets. Experimental results indicate that SALIENT, running on a single Xilinx Alveo U280 device, delivers an average throughput of 546 million bases/second, outperforming the state- of-the-art minimap2 software by 40x, and Bowtie2 by up to 107 x, with a similar or slightly better (~O.l %-0.5 %) alignment and error (false negative/positive) rate. Compared to the existing ungapped FPGA aligners [1]–[4], SALIENT has 9.4-18x higher throughput/Watt, while compared to the gapped aligners [5], [6], it is 28–35 x better. SALIENT achieves 7.6 x higher throughput than Illumina DRAGEN Bio-IT Platform [7].

The sheer amount of genomic sequencing data generated daily that requires time-sensitive processing for downstream analysis calls for accelerating the bioinformatics pipelines. Previous studies mainly have attempted accelerating the alignment stage, leaving the other pipeline stages as performance bottlenecks. In this work, we propose the first FPGA-based framework dubbed FAST to accelerate the stages that deal with sequence trimming, in particular adapter and primer removal. FAST supports a comprehensive set of functionalities and is convenient to use by operating on standard genomics data formats. The proposed framework is fully configurable and supports variety of runtime settings. It surpasses the state-of-the-art widely-used adapter trimmer (fastp) by 4.7×–29.4× speed-up, with 10.1×–54.9 less energy, respectively. For clipping primers, which with current existing tool (iVar) accounts for ∼50% of SARS-CoV-2 analysis pipeline, FAST achieves up to 62× speed-up in trimming the virus sequences with a low FPGA resource utilization of 12%.

This paper conducts a design space exploration of placing general purpose RISCV cores within the DDR DRAM hierarchy to boost the performance of important data analytics applications in the datacenter. We investigate the hardware (where? how many? how to interface?) and software (how to place data? how to map computations?) choices for placing these cores within the rank, chip, and bank of the DIMM slots to take advantage of the locality vs. parallelism trade-offs. We use the popular MapReduce paradigm, normally used to scale out workloads across servers, to scale in these workloads into the DDR DRAM hierarchy. We evaluate the design space using diverse off-the-shelf Apache Spark Workloads to show the pros-and-cons of different hardware placement and software mapping strategies. Results show that bank-level RISCV cores can provide tremendous speedup (up to 363X) for the offload-able parts of these applications, amounting to 14X speedup overall in some applications. Even in the non-amenable applications, we get at least 31% performance boost for the entire application. To realize this, we incur an area overhead of 4% at the bank level, and increase in temperature of < 4°C over the chip averaged over all applications.

Emerging resistive memory (RRAM) based crossbar array is a promising technology to accelerate neural network applications. RRAM-based CNN accelerators support a high-degree of intra-layer and inter-layer parallelism. The intra-layer parallelism duplicates kernels for each network layer while the inter-layer parallelism allows execution of each layer when a portion of input data is available. However, previously proposed RRAM-based accelerators do not leverage data sharing between duplicate kernels leading to significant idleness of crossbar arrays during inference. This shared data creates data dependencies that stall the processing of the next layer in the pipeline. To address these issues, we propose Fine-grained Parallel RRAM Architecture (FPRA), a novel architectural design, to improve parallelism for pipeline-enabled RRAM-based accelerators. FPRA addresses the data sharing issue with kernel batching and data sharing aware memory. Kernel batching rearranges the layout of the kernels and minimizes the data dependencies created by the input shared data. The data sharing aware memory uniformly buffers the input and output data for each layer, efficiently dispatching data to duplicate kernels while reducing the amount of data transferred between layers. We evaluate FPRA on eight popular image recognition CNN models with various configurations in a cycle-accurate simulator. We find that FPRA manages to achieve 2.0 $\times$ average latency speedup, and 2.1 $\times$ average throughput increase, as compared to the state-of-the-art RRAM-based accelerators.

In-situ approaches process data very close to the memory cells, in the row buffer of each subarray. This minimizes data movement costs and affords parallelism across subarrays. However, current in-situ approaches are limited to only row-wide bitwise (or few-bit) operations applied uniformly across the row buffer. They impose a significant overhead of multiple row activations for emulating 32-bit addition and multiplications using bitwise operations and cannot support operations with data dependencies or based on predicates. Moreover, with current peripheral logic, communication among subarrays is inefficient, and with typical data layouts, bits in a word are not physically adjacent. The key insight of this work is that in-situ, single-word ALUs outperform in-situ, parallel, row-wide, bitwise ALUs by reducing the number of row activations and enabling new operations and optimizations. Our proposed lightweight access and control mechanism, Fulcrum, sequentially feeds data into the single-word ALU and enables operations with data dependencies and operations based on a predicate. For algorithms that require communication among subarrays, we augment the peripheral logic with broadcasting capabilities and a previously-proposed method for low-cost inter-subarray data movement. The sequential processor also enables overlapping of broadcasting and computation, and reuniting bits that are physically adjacent. In order to realize true subarray-level parallelism, we introduce a lightweight column-selection mechanism through shifting one-hot encoded values. This technique enables independent column selection in each subarray. We integrate Fulcrum with Compress Express Link (CXL), a new interconnect standard. Fulcrum with one memory stack delivers on average (up to) 23.4 (76) speedup over a server-class GPU, NVIDIA P100, with three stacks of HBM2 memory, (ii) 70 (228) times speedup per memory stack over the GPU, and (iii) 19 (178.9) times speedup per memory stack over an ideal model of the GPU, which only accounts for the overhead of data movement.

This paper proposes an energy-efficient deep inmemory architecture for NAND flash (DIMA-F) to perform machine learning and inference algorithms on NAND flash memory. Algorithms for data analytics, inference, and decision-making require processing of large data volumes and are hence limited by data access costs. DIMA-F achieves energy savings and throughput improvement for such algorithms by reading and processing data in the analog domain at the periphery of NAND flash memory. This paper also provides behavioral models of DIMA-F that can be used for analysis and large scale system simulations in presence of circuit non-idealities and variations. DIMA-F is studied in the context of linear support vector machines and knearest neighbor for face detection and recognition, respectively. An estimated 8×-to-23× reduction in energy and 9×-to-15× improvement in throughput resulting in EDP gains up to 345× over the conventional NAND flash architecture incorporating an external digital ASIC for computation.

In the years between now and 2020, we should expect continued exponential data growth [15][16]. A number of ongoing advances in storage: the transition to solid-state drives (SSDs), the scaling of NAND flash capacity, and advanced silicon packaging techniques will dramatically increase the capacity of storage subsystems over the same timeframe. This will significantly reduce the ratio of storage bandwidth to storage density. Consequently, the majority of data in 2020 will either be cold or will require near-memory acceleration to pull rich information out of the sea of big data. We argue that, increasingly over time, value lies not merely in the size of the data, but rather in what one can do with it.

In this paper, we propose the concept of compute memory, where computation is deeply embedded into the memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute memory exploits the relaxed precision and linearity requirements of pattern recognition applications. System-level simulations incorporating various deterministic errors from analog signal chain demonstrates the limited accuracy of analog processing does not significantly degrade the system performance, which means the probability of pattern detection is minimally impacted. The estimated energy saving is 63 % as compared to the conventional system with standard embedded memory and parallel processing architecture, for 256×256 target image.

In this work, 65nm NOR flash memory is used for an evaluation of data retention and impact on cell charge based on varying levels of exposure to x-ray waves. A sample of 100 fully tested and configured units were programmed with a physical checkerboard pattern (half programmed, half erased) and exposed to conditions found in industrial x-ray stations. Readouts of the data pattern were done at various stages throughout the experiment and a comparison of cell Vt was performed on a population of worst case cells (lowest Vt on programmed cells, highest Vt on erased cells). Data was collected on a bit by bit basis and plotted as a cumulative probability function. Bakes were also performed to introduce any potential defects not seen initially as part of the exposure - and the readout data was collected for this stage as well. Results indicated there is a correlation on the amount of charge gain and loss seen based on the amount of total radiation incident upon the cells in extreme conditions.