A complete strategy to manage dummy fills inside and underneath a large spectrum of integrated RF inductors realized in a 0.13 mum CMOS technology using a Damascene Copper Back End of Line (BEOL) is presented here. The main motivation of this paper is first to evaluate through a Design Of Experiment (DOE) modeling, the impact on RF inductor performances of dummy fills inserted inside or underneath the coils, and then determine the right metal fill density to insert to be compliant with Digital metal density rules without degrading their electrical performances.

A complete strategy to manage dummy fills inside a large spectrum of integrated RF inductors realized in a 0.13 mum CMOS technology using a dual damascene copper back end of line (BEOL) is presented here. Thanks to the developed test structures, their RF characterization, and a design of experiment (DOE) modeling analysis, it has been possible to determine the right metal fill density to insert inside inductors in order to be compliant with digital metal density rules without degrading their electrical performances.

This paper describes realization and characterization of SrTiO3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors in order to realize a high pass filter. Surface capacitance achieved is 10nF/mm2 with capacitance value of 1.2nF. The process for STO MIM fabrication does not exceed 400°C, which is compatible with interconnections. Typical K and dielectric losses values obtained are, respectively 110% and 2%. Yield obtained reaches 83% for capacitors. A functional high pass filter using these STO capacitors was realized in this study. It exhibits a cut-off frequency at 6.5kHz and a constant gain at higher frequencies of −1.3dB.

This paper describes realization and characterization of SrTiO3 (STO) high k MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors