RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, integration has driven the wireless business to achieve appropriate cost and form factor, and CMOS Silicon-on-Insulator (SOI) was adopted about 10 years ago and is now the dominant technology for Radio Frequency Switches (RF SW) in RF FEMs for cell phones and Wi-Fi [1]. While RF SW performances integrated on RF SOI technologies have exceeded what was feasible using GaAs technologies, 6G systems require even more stringent performances and consequently RF SOI technologies must continue to be improved. In this paper, the optimization of an advanced 200 mm RF SOI technology, which achieves a record $R_{\text{on}} \times C_{\text{off}}$ of 60 fs by introducing 65 nm gate length at the Front End of the Line (FEOL) to reduce the channel resistance, is proposed and discussed. Furthermore, an innovative air gap process option at the Back End of the Line (BEOL) is proposed to achieve parasitic capacitance reduction.

Aluminum nitride (AlN)-based acoustic filters are key devices of radio-frequency communications. However, the performance of electroacoustic resonators remains limited by the crystalline quality of the piezoelectric AlN material. An innovative material strategy that combines different types of materials (2D and 3D materials) and growth techniques is presented here to enhance the crystalline quality of thick AlN films grown on silicon-based substrates. Building upon previous works showing the efficacy of 2D MoS2 in sputtered-AlN texturing, this paper demonstrates how an in situ thermochemical treatment of the sputtered-AlN/MoS2 seed layers succeeded by a metal organic vapor phase epitaxy (MOVPE) AlN regrowth significantly enhances the crystalline quality of the AlN layer and avoids the detrimental stack delamination at the weak AlN/MoS2 interface. This paper shows that a delicate balance in the thickness of the sputtered-AlN film should be found to facilitate species diffusion toward the underlying MoS2 without compromising its texturizing properties for the subsequent MOVPE AlN regrowth. The sputtered-AlN/MoS2 seed layers involve a nanometric AlN film of less than 5 nm deposited onto three monolayers of MoS2. The heat treatment induces an unexpected chemical and structural nanometric reorganization at the interface, converting the initial lamellar MoS2 film into a discontinuous covalently bonded MoNxOy film, followed by the appearance of metallic Mo nanoparticles at an elevated temperature. Subsequent MOVPE AlN regrowth on the annealed seed layer stacks enables the growth of thick AlN films of up to 600 nm with a mosaicity of less than 0.3 degrees without delamination or cracks. This approach not only facilitates the integration of thick AlN films on Si-based wafers but also opens avenues for growing III-N or other 3D materials on Si through the intercalation of 2D materials.

This paper presents two methods to improve the reliability and the melting/quench behavior of phase change materials (PCM) used in radiofrequency (RF) switches. Results show benefits of the addition of an aluminum nitride heat spreading layer and the reduction of the distance between the substrate and the PCM. The reduction of the PCM cooling time shown in simulations and the power handling improvement observed in measurements on series structures support our proposed designs of GeTe based switches with RF gaps lengths over 4 mu m, allowing the power handling going to reach 31dBm in both ON and OFF states.

This paper proposes an innovative hybrid package integration strategy compatible with silicon- based technologies. It is evaluated beyond 200 GHz by the integration of a WR3 back-to-back waveguide-to-suspended stripline transition designed in BiCMOS technology, relying on metallic split-block package and organic laminate substrate. Simulated insertion loss below 3 dB is observed in the 220-320 GHz frequency band, competing with reported traditional solutions using III-V substrates. The achieved performances lead to promising perspectives for low-cost silicon packaging solutions beyond 200 GHz.

In this Letter, we propose an approach to improve the packaging of electro-optical transceivers based on silicon photonics through the development of a glass interposer. This assembly platform integrates polymer optical waveguides and an integrated turning mirror that vertically redirect the optical signal in the plane of the interposer to the grating coupler of a flip-chipped photonic integrated circuit (PIC). A distinctive feature of the proposed packaging scheme is to use a conventional flip-chip technique without active alignment. Functionalities are completed with a copper redistribution layer that supports the routing of DC to millimeter wave (mmW) signals to drive the PIC. The measured loss in polymer waveguides is 1.92 dB/cm at 1310 nm, and the coupling losses associated with light propagation through the turning mirror and the PIC grating coupler are 18.7 dB. Coplanar mmW waveguides are structured on the glass interposer by cold laser ablation, yielding an attenuation of 0.3 dB/mm at 58 GHz. The most important outcome of this work is that the coupling of the optical signal from the interposer to the PIC is experimentally established. We also assessed the mmW performance of coplanar waveguides through the validation of the interposer to PIC and PIC to the interposer transition.

Aluminum nitride (AlN) is a wide bandgap material used in acoustic devices, piezo- micro-electromechanical system and is promising for other electronic applications. However, for most applications, the AlN crystalline quality obtained by PVD or MOCVD is insufficient, and suitable growth substrates providing an adapted lattice match and coefficient of thermal expansion are limited. Alternatively, monocrystalline AlN wafers are not yet available in 200/300 mm sizes and suffer from high costs and quality issues. Here, we propose a novel approach involving a two-dimensional transition metal dichalcogenide (TMD) material as a seed layer, which displays an excellent lattice matching with AlN (>98%) allowing a strong enhancement in the c axis texture of sputtered AlN layers on Si(100)/SiO2 thermal oxide (500 nm) substrates. We have successfully demonstrated an eightfold improvement of the AlN (002) rocking curve compared to reference samples grown on thermal SiO2, thus providing a relevant and cost-effective process for the large-scale deployment of high-quality III-N materials on silicon-based substrates.

In this paper, an innovative packaging integration strategy compatible with Silicon-based technologies is proposed. It is assessed beyond 200 GHz by the integration of a BiCMOS WR3 back-to-back waveguide (WG) to suspended stripline (SSL) transition in organic laminate substrate. An insertion loss below 3 dB is obtained in the 220-320 GHz band, competing with traditional solutions using III-V substrates. Achieved performances are promising and could enable sub-THz volume-manufacturing packaging solutions for Silicon technologies.

Reduction of parasitic front-end capacitance is one of the key factors to improve the performance of RF applications. In this work, we report the development of an atypical gate architecture allowing the reduction of the source/drain overlap capacitances of a PD-SOI n-MOS transistor. After presenting the process flow and monitoring methods, we discuss the low frequency and RF electrical results such as C OFF , R ON , RF Vmax .

Two-dimensional (2D) metal nitrides nanosheets are new emerging materials with potential applications in electronics, energy storage or conversion efficiency. In this paper, we report the synthesis of molybdenum nitride by nitriding molybdenum disulfide (MoS2) via a 700 °C ammonia (NH3) reactive heat treatment. A well-controlled uniform MoS2 thin film was prepared by Atomic Layer Deposition (ALD). The progressive MoS2 nitriding reaction has been demonstrated by in situ reflectance measurements. These results have been confirmed by Raman and X-Ray Photoelectron Spectrometry (XPS). This method paves the way to a new potential route to the synthesis Mo nitride nanosheets obtained from a well-controlled uniform MoS2 thin film deposited by ALD.

Over the years, RFSOI has emerged as dominant technology for building RF FEM modules with optimum cost and performance. RFSOI switches are typically designed using thick gate oxides with biasing up to 3. 3V to deliver minimum RON x COFF. With the strong push of operating digital devices at lower voltages, it would become necessary to evaluate the performance of the switch under such operating conditions. In this paper, we analyze the impact of RON x COFF of the switch in 200mm RFSOI technology, under scaled bias conditions and propose path for device optimization.

This paper reports the integration and characterization of germanium telluride (GeTe) phase-change material (PCM)-based RF switches in series configuration with a 89 μm wide PCM element to address sub-6G power handling requirements. Switching conditions using indirect heating, as well as small-and large-signal measurements are performed in this work. Devices handle power up to 37 dBm and 29 dBm respectively in ON-and OFF-state at 915 MHz. These results estimate for the first time the performances of such wide GeTe switches compatible with cellular applications and investigate technological improvement guidelines.

Two-dimensional (2D) metal nitrides are new emerging materials with potential applications in electronics, energy storage, or conversion efficiency. In this paper, we report the synthesis of molybdenum nitride by nitriding molybdenum disulfide (MoS2) via a 700 °C ammonia (NH3) reactive heat treatment. A well-controlled uniform MoS2 thin film was prepared by atomic layer deposition (ALD). The progressive MoS2 nitriding reaction has been demonstrated and monitored by in situ reflectance measurements. These results have been confirmed by Raman and x-ray photoelectron spectrometry. This method paves the way to a new potential route to the synthesis of Mo nitride obtained from a well-controlled uniform 2D-MoS2 thin film deposited by ALD.

This article analyses the introduction of airgaps in the interconnect network of silicon-on-insulator (SOI)-CMOS-based RF switches to significantly reduce the OFF-state capacitance ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ without degrading the ON-state resistance ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . Based on the 130-nm node of an existing RF-SOI-CMOS technology, an accurate ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ evaluation is performed by calculating the respective contributions of interconnects and the intrinsic transistor separately. The impact of the relative airgap volume is simulated and results in an ultimate ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ reduction of 24.6% when the intermetal dielectric is completely replaced by air. It is shown that most of the reduction in ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ is achieved by introducing airgap at the first metal level. The airgap approach is verified experimentally by partially eliminating the interconnect dielectric of RF switches in postprocess etching steps. A measured ${C}_{ \mathrm{\scriptscriptstyle OFF}}$ improvement of 21.7 (7.2%) and 18.3 fF/mm (6.3%) is demonstrated for 0.14- and 0.16- $\mu \text{m}$ gate length transistors, for which the airgap volume is only partial.

RF Front-End Modules (FEM) for both smartphones and infrastructure are today deployed thanks to several technologies (GaAs, GaN, LDMOS, SiGe and RFSOI). RFSOI technology has already completely replaced GaAs for RF switches integration, but due to its very good cost/performances trade-off, RFSOI technology is also a good candidate to enable RF FEM System On Chip (LNA, PA and RF Switch on the same die). We present in this paper the development on 300-mm wafer of a cost-optimized 40-nm PDSOI technology targeting 5G wireless networks from sub-6 GHz up to mmW frequencies. Elementary devices and circuits measurements are reviewed to illustrate achievable performances.

This paper investigates the reduction of the off-state capacitance (C OFF ) of SOI-CMOS RF switches induced by the introduction of air microcavity in the back-end interconnection network. A detailed methodology combining electromagnetic and semiconductor transport simulations is used to separately evaluate the respective contributions of the interconnects and junction capacitances. A baseline switch and an optimized version of the same are studied to evaluate their ability to take advantage of air microcavities. Simulations show a reduction of 73 fF/mm regardless of the switch structure considered, resulting in a 24.6% and 30.6% improvement in C OFF for baseline and optimized switches, respectively, bringing the optimized version to a 60fs record Ron × Coff. This concept was experimentally implemented using a partial etch process that resulted in a reduction of 21.7 fF/mm, i.e., 7.2%. Finally, the implementation of a more isotropic and selective etching process using HF in vapor phase is shown to approach the optimal configuration of air microcavities.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{ON}}\times C_{\text{OFF}}$</tex> of 78 fs with a breakdown voltage of 3.7 V.

RF Front End Modules (FEMs) are currently achieved using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has been adopted 10 years ago and is now the dominant technology for RF switches in RF FEMs for cell phones and WiFi [1]. While current performances available on RF SOI technology have been exceeding what was feasible using GaAs one, new cellular system requirements ask even more stringent performances and consequently RF SOI technology must continue to improve. In this paper, we review and discuss the optimization of an advanced 200 mm RF SOI technology achieving $R_{\text{ON}}\times C_{\text{OFF}}$ of 78 fs with a breakdown voltage of 3.7 V.