ion levels, ranging from behavioral to structural. HIS contains general algorithms for scheduling and allocation which can handle behavioral, sequential, concurrent, and structural constructs, and user-defined constraints. Different algorithms, specially tuned to the abstraction level of the description, are used in order to synthesize designs efficiently for execution time and memory usage. The scheduling and allocation algorithms in HIS are based on global techniques such as global data-flow analysis and path analysis. The scheduler is able to find the exact minimum number of control steps required by a design under user constraints. The resource-sharing algorithms are more general than previous algorithms in determining the set of elements that can be shared. Global data-flow analysis, path analysis, and BDDs are used to derive the exact maximum set of sharable data-path elements. use of HIS were 1) efficient high-level synthesis algorithms, 2) a rich set of directives for controlling the synthesis process, and 3) integration with the BooleDozer logic synthesis system. The capabilities of the system have proved to be powerful enough for it to be used in production as part of the synthesis methodology, and in domains for which it was not originally intended, such as a front end for HIS is able to synthesize VHDL descriptions in different Among the main characteristics required for production IBM J. RES. DEVELOP. VOL. 39 NO. 112 JANUARYIMARCH 1995 verification and cycle simulation. Several CMOS chips, ranging from small to large, have been produced using HIS. Acknowledgments The authors thank Kurt Carpenter, Pete Osler, and Coby Sella for being patient early users of the system and for many helpful suggestions for improving its practicality. BooleDozer is a trademark of International Business Machines Corporation.

This paper addresses the lifetime characteristics of standard and synthetic spin valves of different PtMn antiferromagnet (AFM) thicknesses and compositions. It shows that loss of magnetoresistance with time at elevated temperature is less pronounced for synthetic structures, for thinner PtMn AFM films exchange-annealed for relatively longer times, and Pt-rich compositions of PtMn, The lifetime temperature T-max is defined as the maximum operating temperature for the spin valve that results in less than a 10% drop in output for a five-year 50% duty cycle. The generalized prediction of lifetime temperature T-max from the more usable unblocked ratio (UBR) point on the UBR-versus-temperature curve is complicated by test conditions and initial H(e)x values. For H(e)x values and reverse field magnitudes for the sheet film spin valve samples tested here, the tolerable UBR was in the 6-8% range, and Tmax values in the 170 degrees -205 degreesC range. Choosing the correct reverse field for DeltaT(b) measurements was important for synthetic structures because of the interaction between the applied field and the coupling field between the inner and outer pinned layers in the synthetic structure. Finished heads show T-max values that are lower by 40 degrees -55 degrees for the five-year 50% duty cycle criterion compared to sheet films. This highlights the importance of processing environments, especially in slider fabrication, and imposes a further restriction on the acceptable sheet film tolerable UBR, reducing it to 3-4%, Activation energies from lifetime tests are in the range 2.2 to 2.6 eV for all samples including finished sliders, which indicates that differences in lifetimes are not associated with large variability in the activation energy of depinning within the PtMn system. The time-dependence of magnetic properties such as interlayer coupling (H-ilc) and coercivity (H-c) of the free layer is very important and exhibits runaway behavior with time. It must be monitored for deleterious effects.

The factors which determine the strength of the magnetic biased field in NiMn/NiFe exchange biased system have been examined. It was found that a strong NiFe (111) texture and columnar growth are essential to obtaining a high exchange field as they facilitate epitaxy between the NiFe and NiMn layers. The application of an amorphous Ta nucleation layer and substrate biasing during NiFe deposition have been found to promote these structures. Fcc NiMn replicates the (111) texture through epitaxial growth on NiFe according to a cube on cube orientation relationship. Upon annealing, atomic ordering takes place in the NiMn layer and gives rise to an exchange biased field. However, a fully L10 ordered structure cannot be achieved at the NiMn/NiFe interface due to the stabilizing effect of fcc NiFe. Away from the interface, the transformation proceeds and the ordered tetragonal unit cell creates a lattice strain within the NiMn film. This strain is relieved by twinning within the NiMn grains of the film. The strength of the exchange field has been found to be closely associated with the density of twins and their proximity to the NiMn/NiFe interface.

The atomic structure across the annealed Ni/Mn/NiFe exchange coupled interface has been studied. NiMn grows epitaxially on NiFe (111) according to a cube on cube orientation relationship. This yields a semi-coherent interface which is made up of atomic ledges. Due to the stabilizing effect of fee NiFe, it was found that the NiMn crystal cannot attain the ordered L1(0) structure thus holding down the strength of the exchange bias field. However, twinning at the interface seemingly helps to assist NiMn ordering.

This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.

The use of modern hardware-description languages in the chip design process has allowed designs to be modeled at higher abstraction levels. More powerful modeling styles, such as register-transfer and behavioral level specifications, have spurred the development of high-level synthesis techniques in both industry and academia, However, despite the many research efforts, the technology is not yet in widespread use in industry. This paper presents the IBM High-Lever Synthesis System (HIS), which is the first such system to be used in production in IBM, HIS synthesizes gate-level networks from VHDL models at various levels of abstraction, The main algorithms, modeling capabilities, and methodology considerations in the HIS system are presented. Results show that HIS is capable of producing implementations comparable to or better than those of the existing methodology, while shortening the design time significantly, The HIS system is currently in production use and evaluation in several IBM sites for processors and peripheral chip designs, as well as being an external commercial product.

Synthesis takes a specification of the functionality of a digital system and a set of constraints and finds a structure that implements the intended behavior and satisfies the constraints. At the algorithmic level, the specification takes the form of an algorithm. This implies that basic implementation decisions have already been made—thus the term algorithmic “description”, introduced in Chapter 1, is used rather than the term “specification.” But, of course, in comparison to the RT-level, many implementation details are left open at the algorithmic level and have to be filled in by automated synthesis.